公开(公告)号：US20170069725A1

公开(公告)日：2017-03-09

申请号：US15122796

申请日：2014-06-26

Applicant: Intel Corporation

Inventor： GOPINATH BHIMARASETTI ,  WALID M. HAFEZ ,  JOODONG PARK ,  WEIMIN HAN ,  RAYMOND E. COTNER ,  CHIA-HONG JAN

IPC: H01L29/36 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/36 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66803 ,  H01L29/66818 ,  H01L29/7853

Abstract: Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.

Abstract translation: 描述了具有掺杂子鳍区域的ω鳍片的非平面半导体器件以及制造具有掺杂子鳍片区域的具有Ω形翅片的非平面半导体器件的方法。 例如，半导体器件包括设置在半导体衬底上方的多个半导体鳍片，每个半导体鳍片具有在突出部分下方的副鳍片部分，子鳍片部分比突出部分窄。 固态掺杂剂源层设置在半导体衬底之上，与子鳍区域共形而不是多个半导体鳍片中的每一个的突出部分。 隔离层设置在固态掺杂剂源层上方和多个半导体鳍片的子鳍片区域之间。 栅极叠层设置在隔离层上方并与多个半导体鳍片中的每一个的突起部分保形。