中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

18 records (took 0.014 seconds)

    RESISTOR BETWEEN GATES IN SELF-ALIGNED GATE EDGE ARCHITECTURE
    1.
    发明申请
    RESISTOR BETWEEN GATES IN SELF-ALIGNED GATE EDGE ARCHITECTURE 审中-公开

    公开(公告)号：US20200043914A1

    公开(公告)日：2020-02-06

    申请号：US16474896

    申请日：2017-03-31

    Applicant: INTEL CORPORATION

    Inventor： ROMAN W. OLAC-VAW ,  WALID M. HAFEZ ,  CHIA-HONG JAN ,  HSU-YU CHANG ,  NEVILLE L. DIAS ,  RAHUL RAMASWAMY ,  NIDHI NIDHI ,  CHEN-GUAN LEE

    IPC: H01L27/06 ,  H01L27/088 ,  H01L49/02 ,  H01L29/06 ,  H01L21/8234

    Abstract: Techniques are disclosed for forming semiconductor structures including resistors between gates on self-aligned gate edge architecture. A semiconductor structure includes a first semiconductor fin extending in a first direction, and a second semiconductor fin adjacent to the first semiconductor fin, extending in the first direction. A first gate structure is disposed proximal to a first end of the first semiconductor fin and over the first semiconductor fin in a second direction, orthogonal to the first direction, and a second gate structure is disposed proximal to a second end of the first semiconductor fin and over the first semiconductor fin in the second direction. A first structure comprising isolation material is centered between the first and second semiconductor fins. A second structure comprising resistive material is disposed in the first structure, the second structure extending at least between the first gate structure and the second gate structure.

    MEMORY CELL HAVING ISOLATED CHARGE SITES AND METHOD OF FABRICATING SAME
    2.
    发明申请
    MEMORY CELL HAVING ISOLATED CHARGE SITES AND METHOD OF FABRICATING SAME 有权
    具有隔离充电位置的存储单元及其制造方法

    公开(公告)号：US20160049418A1

    公开(公告)日：2016-02-18

    申请号：US14779938

    申请日：2013-06-25

    Applicant: INTEL CORPORATION

    Inventor： TING CHANG ,  CHIA-HONG JAN ,  WALID M. HAFEZ

    IPC: H01L27/115 ,  H01L29/792 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28

    CPC classification number: H01L27/11563 ,  G11C16/0475 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/42348 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

    Abstract: Memory cells having isolated charge sites and methods of fabricating memory cells having isolated charge sites are described. In an example, a nonvolatile charge trap memory device includes a substrate having a channel region, a source region and a drain region. A gate stack is disposed above the substrate, over the channel region. The gate stack includes a tunnel dielectric layer disposed above the channel region, a first charge-trapping region and a second charge-trapping region. The regions are disposed above the tunnel dielectric layer and separated by a distance. The gate stack also includes an isolating dielectric layer disposed above the tunnel dielectric layer and between the first charge-trapping region and the second charge-trapping region. A gate dielectric layer is disposed above the first charge-trapping region, the second charge-trapping region and the isolating dielectric layer. A gate electrode is disposed above the gate dielectric layer.

    Abstract translation: 描述了具有隔离电荷位置的存储单元和制造具有隔离电荷位点的存储单元的方法。 在一个示例中，非易失性电荷陷阱存储器件包括具有沟道区，源极区和漏极区的衬底。 栅极堆叠设置在衬底上方，在沟道区域上方。 栅堆叠包括设置在沟道区上方的隧道介电层，第一电荷俘获区和第二电荷俘获区。 这些区域设置在隧道介电层上方并分开一段距离。 栅堆叠还包括设置在隧道介电层上方和第一电荷俘获区与第二电荷俘获区之间的隔离电介质层。 栅电介质层设置在第一电荷捕获区，第二电荷捕获区和隔离电介质层的上方。 栅极电极设置在栅极电介质层的上方。

    ANTIFUSE ELEMENT USING SPACER BREAKDOWN
    3.
    发明申请
    ANTIFUSE ELEMENT USING SPACER BREAKDOWN 审中-公开

    公开(公告)号：US20180218977A1

    公开(公告)日：2018-08-02

    申请号：US15935838

    申请日：2018-03-26

    Applicant: INTEL CORPORATION

    Inventor： TING CHANG ,  CHIA-HONG JAN ,  WALID M. HAFEZ

    IPC: H01L23/525 ,  G11C17/14 ,  H01L27/112 ,  H01L27/102 ,  H01L23/62 ,  G11C17/16

    CPC classification number: H01L23/5252 ,  G11C11/005 ,  G11C17/143 ,  G11C17/16 ,  G11C17/165 ,  H01L23/62 ,  H01L27/1021 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, including both non-volatile and volatile memories. The memory circuitry employs an antifuse scheme that includes an array of 1T bitcells, wherein each bitcell effectively contains one gate or transistor-like device that provides both an antifuse element and a selector device for that bitcell. In particular, the bitcell device has asymmetric trench-based source/drain contacts such that one contact forms a capacitor in conjunction with the spacer and gate metal, and the other contact forms a diode in conjunction with a doped diffusion area and the gate metal. The capacitor serves as the antifuse element of the bitcell, and can be programmed by breaking down the spacer. The diode effectively provides a Schottky junction that serves as a selector device which can eliminate program and read disturbs from bitcells sharing the same bitline/wordline.

    PLANAR DEVICE ON FIN-BASED TRANSISTOR ARCHITECTURE
    4.
    发明申请
    PLANAR DEVICE ON FIN-BASED TRANSISTOR ARCHITECTURE 审中-公开
    基于晶圆的晶体管架构的平面设备

    公开(公告)号：US20160276346A1

    公开(公告)日：2016-09-22

    申请号：US15167006

    申请日：2016-05-27

    Applicant: INTEL CORPORATION

    Inventor： WALID M. HAFEZ ,  PETER J. VANDERVOORN ,  CHIA-HONG JAN

    IPC: H01L27/088 ,  H01L29/16 ,  H01L29/161 ,  H01L21/8234

    CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/1608 ,  H01L29/161

    Abstract: Techniques are disclosed for forming a planar-like transistor device on a fin-based field-effect transistor (finFET) architecture during a finFET fabrication process flow. In some embodiments, the planar-like transistor can include, for example, a semiconductor layer which is grown to locally merge/bridge a plurality of adjacent fins of the finFET architecture and subsequently planarized to provide a high-quality planar surface on which the planar-like transistor can be formed. In some instances, the semiconductor merging layer can be a bridged-epi growth, for example, comprising epitaxial silicon. In some embodiments, such a planar-like device may assist, for example, with analog, high-voltage, wide-Z transistor fabrication. Also, provision of such a planar-like device during a finFET flow may allow for the formation of transistor devices, for example, exhibiting lower capacitance, wider Z, and/or fewer high electric field locations for improved high-voltage reliability, which may make such devices favorable for analog design, in some instances.

    Abstract translation: 公开了在finFET制造工艺流程期间在基于鳍片的场效应晶体管（finFET）架构上形成平面状晶体管器件的技术。 在一些实施例中，平面状晶体管可以包括例如半导体层，该半导体层被生长以局部地合并/桥接finFET架构的多个相邻鳍片，并且随后被平坦化以提供高质量的平面表面，平面 形晶体管。 在一些情况下，半导体合并层可以是桥接外延生长，例如包括外延硅。 在一些实施例中，这样的平面状器件可以辅助例如模拟，高电压，宽Z晶体管制造。 此外，在finFET流动期间提供这样的平面状器件可以允许形成晶体管器件，例如，显示出更低的电容，更宽的Z和/或更少的高电场位置，以改善高电压可靠性，其可以 在某些情况下，使这种设备有利于模拟设计。

    Low Leakage Non-Planar Access Transistor for Embedded Dynamic Random Access Memory (eDRAM)
    5.
    发明申请
    Low Leakage Non-Planar Access Transistor for Embedded Dynamic Random Access Memory (eDRAM) 有权
    用于嵌入式动态随机存取存储器（eDRAM）的低泄漏非平面存取晶体管

    公开(公告)号：US20160197082A1

    公开(公告)日：2016-07-07

    申请号：US14912890

    申请日：2013-09-27

    Applicant: INTEL CORPORATION

    Inventor： JOODONG PARK ,  GOPINATH BHIMARASETTI ,  RAHUL RAMASWAMY ,  CHIA-HONG JAN ,  WALID M. HAFEZ ,  JENG-YA D. YEH ,  CURTIS TSAI

    IPC: H01L27/108

    CPC classification number: H01L27/10826 ,  H01L27/10808 ,  H01L27/10879 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7854

    Abstract: Low leakage non-planar access transistors for embedded dynamic random access memory (eDRAM) and methods of fabricating low leakage non-planar access transistors for eDRAM are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate and including a narrow fin region disposed between two wide fin regions. A gate electrode stack is disposed conformal with the narrow fin region of the semiconductor fin, the gate electrode stack including a gate electrode disposed on a gate dielectric layer. The gate dielectric layer includes a lower layer and an upper layer, the lower layer composed of an oxide of the semiconductor fin. A pair of source/drain regions is included, each of the source/drain regions disposed in a corresponding one of the wide fin regions.

    Abstract translation: 描述了用于嵌入式动态随机存取存储器（eDRAM）的低泄漏非平面存取晶体管和用于制造用于eDRAM的低泄漏非平面存取晶体管的方法。 例如，半导体器件包括设置在衬底上方并且包括设置在两个宽鳍片区域之间的窄鳍区域的半导体鳍片。 栅电极堆叠被配置为与半导体鳍片的窄鳍区域共形，栅电极堆叠包括设置在栅介质层上的栅电极。 栅介质层包括下层和上层，下层由半导体鳍片的氧化物构成。 包括一对源极/漏极区域，每个源极/漏极区域布置在相应的一个宽鳍片区域中。

    NON-PLANAR SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED FIN WITH TOP BLOCKING LAYER
    8.
    发明申请
    NON-PLANAR SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED FIN WITH TOP BLOCKING LAYER 有权
    具有顶部阻挡层的自对准FIN的非平面半导体器件

    公开(公告)号：US20160056293A1

    公开(公告)日：2016-02-25

    申请号：US14780218

    申请日：2013-06-26

    Applicant: INTEL CORPORATION

    Inventor： JENG-YA D. YEH ,  CHIA-HONG JAN ,  WALID M. HAFEZ ,  JOODONG PARK

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423

    CPC classification number: H01L29/7851 ,  H01L29/42368 ,  H01L29/66795 ,  H01L29/785

    Abstract: Non-planar semiconductor devices having self-aligned fins with top blocking layers and methods of fabricating non-planar semiconductor devices having self-aligned fins with top blocking layers are described. For example, a semiconductor structure includes a semiconductor fin disposed above a semiconductor substrate and having a top surface. An isolation layer is disposed on either side of the semiconductor fin, and recessed below the top surface of the semiconductor fin to provide a protruding portion of the semiconductor fin. The protruding portion has sidewalls and the top surface. A gate blocking layer has a first portion disposed on at least a portion of the top surface of the semiconductor fin, and has a second portion disposed on at least a portion of the sidewalls of the semiconductor fin. The first portion of the gate blocking layer is continuous with, but thicker than, the second portion of the gate blocking layer. A gate stack is disposed on the first and second portions of the gate blocking layer.

    Abstract translation: 描述了具有顶部阻挡层的自对准翅片的非平面半导体器件以及制造具有顶部阻挡层的具有自对准翅片的非平面半导体器件的方法。 例如，半导体结构包括设置在半导体衬底之上并具有顶表面的半导体鳍片。 隔离层设置在半导体鳍片的任一侧，并且在半导体鳍片的顶表面下方凹进，以提供半导体鳍片的突出部分。 突出部具有侧壁和顶面。 栅极阻挡层具有设置在半导体鳍片的顶表面的至少一部分上的第一部分，并且具有设置在半导体鳍片的至少一部分侧壁上的第二部分。 栅极阻挡层的第一部分与栅极阻挡层的第二部分连续但是比第二部分更厚。 栅极堆叠设置在栅极阻挡层的第一和第二部分上。

    HIGH-VOLTAGE TRANSISTOR WITH SELF-ALIGNED ISOLATION
    9.
    发明申请
    HIGH-VOLTAGE TRANSISTOR WITH SELF-ALIGNED ISOLATION 审中-公开

    公开(公告)号：US20180248039A1

    公开(公告)日：2018-08-30

    申请号：US15754151

    申请日：2015-09-25

    Applicant: INTEL CORPORATION

    Inventor： WALID M. HAFEZ ,  CHIA-HONG JAN

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08

    CPC classification number: H01L29/7835 ,  H01L29/0653 ,  H01L29/0873 ,  H01L29/66545 ,  H01L29/785

    Abstract: A high-voltage transistor structure is provided that includes a self-aligned isolation feature between the gate and drain. Normally, the isolation feature is not self-aligned. The self-aligned isolation process can be integrated into standard CMOS process technology. In one example embodiment, the drain of the transistor structure is positioned one pitch away from the active gate, with an intervening dummy gate structure formed between the drain and active gate structure. The dummy gate structure is sacrificial in nature and can be utilized to create a self-aligned isolation recess, wherein the gate spacer effectively provides a template for etching the isolation recess. This self-aligned isolation forming process eliminates a number of the variation and dimensional constraints attendant non-aligned isolation forming techniques, which in turn allows for smaller footprint and tighter alignment so as to reduce device variation. The structure and forming techniques are compatible with both planar and non-planar transistor architectures.

Patent Agency Ranking