A memory device and a method for fabricating the same are provided. A memory device includes a tunneling dielectric layer located on a substrate. The floating gate includes a first doped portion on the tunneling dielectric layer and a second doped portion located on the first doped portion. The first doped portion includes a first dopant and a second dopant, and the second doped portion includes the first dopant. The grain size of the first doped portion is smaller than the grain size of the second doped portion, and the grain size of the first doped portion is between 150 Å to 200 Å. The memory device further includes an inter-gate dielectric layer on the floating gate and a control gate on the inter-gate dielectric layer. A source region and a drain region are located in the substrate besides sidewalls of the floating gate.