公开(公告)号：US12027584B2

公开(公告)日：2024-07-02

申请号：US17855300

申请日：2022-06-30

Applicant: MACRONIX International Co., Ltd.

Inventor： Jeng Hwa Liao ,  Zong-Jie Ko ,  Hsing-Ju Lin ,  Jung-Yu Shieh ,  Ling-Wuu Yang

IPC: H01L29/08 ,  H01L21/265 ,  H01L21/266 ,  H01L29/06 ,  H01L29/10 ,  H01L29/167 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/167 ,  H01L29/66598 ,  H01L29/7833 ,  H01L21/266

Abstract: A transistor structure including a substrate, a gate structure, first pocket doped regions, second pocket doped regions, and source/drain extension regions, and source/drain regions is provided. The gate structure is located on the substrate. The first pocket doped regions are located in the substrate aside the gate structure. A dopant of the first pocket doped region includes a group IVA element. The second pocket doped regions are located in the substrate aside the gate structure. A depth of the second pocket doped region is greater than a depth of the first pocket doped region. The source/drain extension regions are located in the first pocket doped regions. The source/drain regions are located in the substrate aside the gate structure. The source/drain extension region is located between the source/drain region and the gate structure.

公开(公告)号：US20170069762A1

公开(公告)日：2017-03-09

申请号：US14845828

申请日：2015-09-04

Applicant: MACRONIX International Co., Ltd.

Inventor： Jeng-Hwa Liao ,  Jung-Yu Shieh ,  Ling-Wuu Yang

IPC: H01L29/788 ,  H01L29/66

CPC classification number: H01L29/40114 ,  H01L29/42324

Abstract: A memory device and a method for fabricating the same are provided. A memory device includes a tunneling dielectric layer located on a substrate. The floating gate includes a first doped portion on the tunneling dielectric layer and a second doped portion located on the first doped portion. The first doped portion includes a first dopant and a second dopant, and the second doped portion includes the first dopant. The grain size of the first doped portion is smaller than the grain size of the second doped portion, and the grain size of the first doped portion is between 150 Å to 200 Å. The memory device further includes an inter-gate dielectric layer on the floating gate and a control gate on the inter-gate dielectric layer. A source region and a drain region are located in the substrate besides sidewalls of the floating gate.

Abstract translation: 提供了一种存储器件及其制造方法。 存储器件包括位于衬底上的隧道电介质层。 浮置栅极包括隧道电介质层上的第一掺杂部分和位于第一掺杂部分上的第二掺杂部分。 第一掺杂部分包括第一掺杂剂和第二掺杂剂，第二掺杂部分包括第一掺杂剂。 第一掺杂部分的晶粒尺寸小于第二掺杂部分的晶粒尺寸，并且第一掺杂部分的晶粒尺寸在150埃到200埃之间。 存储器件还包括浮置栅极上的栅极间介质层和栅极间电介质层上的控制栅极。 除了浮置栅极的侧壁之外，源极区和漏极区位于衬底中。

公开(公告)号：US20160110859A1

公开(公告)日：2016-04-21

申请号：US14516961

申请日：2014-10-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Tuung Luoh ,  Hsiao-Leng Li ,  Ling-Wuu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: G06T7/00

CPC classification number: G06T7/001 ,  G06T7/12 ,  G06T2207/10056 ,  G06T2207/30148

Abstract: An inspection method for contact by die to database is provided. In the method, a plurality of raw images of contacts in a wafer is obtained, and a plurality of locations of the raw images is then recoded to obtain a graphic file. After that, the graphic file is aligned on a design database of the chip. An image extraction is then performed on the raw images to obtain a plurality of image contours of the contacts. Thereafter, a difference in critical dimension between the image contours of the contacts and corresponding contacts in the design database are measured in order to obtain the inspection result for contacts in the wafer.

Abstract translation: 提供了一种用于与数据库接触的检查方法。 在该方法中，获得晶片中的接触的多个原始图像，然后重新编码原始图像的多个位置以获得图形文件。 之后，图形文件在芯片的设计数据库上对齐。 然后对原始图像执行图像提取以获得联系人的多个图像轮廓。 此后，为了获得晶片中的触点的检查结果，测量了触点的图像轮廓与设计数据库中的对应触点之间的临界尺寸差异。

公开(公告)号：US09236497B2

公开(公告)日：2016-01-12

申请号：US14107935

申请日：2013-12-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Jeng-Hwa Liao ,  Jung-Yu Shieh ,  Ling-Wuu Yang

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L29/788 ,  H01L21/02 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/423 ,  H01L21/3215 ,  H01L21/265

CPC classification number: H01L29/7883 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/26586 ,  H01L21/26593 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/3215 ,  H01L21/32155 ,  H01L21/76224 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42376 ,  H01L29/7781

Abstract: The method for fabricating a semiconductor device is provided. A doped semiconductor layer is formed over the substrate. The doped semiconductor layer is patterned to form a plurality of doped semiconductor patterns. An implantation process is performed to implant a dopant into the doped semiconductor patterns. A process temperature of the implantation process is no more than about −50° C. The dopants of the implantation process and the doped semiconductor patterns have the same conductivity type.

Abstract translation: 提供了制造半导体器件的方法。 在衬底上形成掺杂半导体层。 图案化掺杂半导体层以形成多个掺杂半导体图案。 执行注入工艺以将掺杂剂注入到掺杂半导体图案中。 注入工艺的工艺温度不超过约-50℃。注入工艺和掺杂半导体图案的掺杂剂具有相同的导电类型。

公开(公告)号：US20150171223A1

公开(公告)日：2015-06-18

申请号：US14107935

申请日：2013-12-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Jeng-Hwa Liao ,  Jung-Yu Shieh ,  Ling-Wuu Yang

IPC: H01L29/788 ,  H01L21/265 ,  H01L29/423 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L29/7883 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/26586 ,  H01L21/26593 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/3215 ,  H01L21/32155 ,  H01L21/76224 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42376 ,  H01L29/7781

Abstract: The method for fabricating a semiconductor device is provided. A doped semiconductor layer is formed over the substrate. The doped semiconductor layer is patterned to form a plurality of doped semiconductor patterns. An implantation process is performed to implant a dopant into the doped semiconductor patterns. A process temperature of the implantation process is no more than about −50° C. The dopants of the implantation process and the doped semiconductor patterns have the same conductivity type.

Abstract translation: 提供了制造半导体器件的方法。 在衬底上形成掺杂半导体层。 图案化掺杂半导体层以形成多个掺杂半导体图案。 执行注入工艺以将掺杂剂注入到掺杂半导体图案中。 注入工艺的工艺温度不超过约-50℃。注入工艺和掺杂半导体图案的掺杂剂具有相同的导电类型。

公开(公告)号：US09006003B1

公开(公告)日：2015-04-14

申请号：US14220993

申请日：2014-03-20

Applicant: MACRONIX International Co., Ltd.

Inventor： Tuung Luoh ,  Chi-Min Chen ,  Ling-Wuu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: H01L21/00 ,  G11C99/00 ,  H01L21/66 ,  G01R31/28

CPC classification number: H01L22/14 ,  G01R31/2851 ,  G06T7/0004 ,  G06T2207/10061 ,  G06T2207/30148 ,  G11C29/006 ,  G11C29/56008 ,  G11C2029/5604

Abstract: A method of detecting bitmap failure associated with physical coordinates is provided. In the method, data of wafer mapping inspection are obtained first, and the data include images of defects in each of layers within a wafer and a plurality of physical coordinates of the defects. Thereafter, a bitmap failure detection is performed to obtain digital coordinates of failure bits within the wafer. The digital coordinates are converted into a plurality of physical locations, and the physical locations are overlapped with the physical coordinates so as to rapidly obtain correlations between the failure bits and the defects.

Abstract translation: 提供了一种检测与物理坐标相关联的位图故障的方法。 在该方法中，首先获得晶片映射检查的数据，并且数据包括晶片内的每个层中的缺陷图像和缺陷的多个物理坐标。 此后，执行位图故障检测以获得晶片内的故障位的数字坐标。 数字坐标被转换成多个物理位置，并且物理位置与物理坐标重叠，以便快速获得故障位与缺陷之间的相关性。

公开(公告)号：US09589086B2

公开(公告)日：2017-03-07

申请号：US14165043

申请日：2014-01-27

Applicant: MACRONIX International Co., Ltd.

Inventor： Tuung Luoh ,  Hsiang-Chou Liao ,  Ling-Wuu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: G06F17/00 ,  G06F17/50 ,  G02B21/00 ,  H01J37/28

CPC classification number: G06F17/5045 ,  G02B21/002 ,  H01J37/28 ,  H01J2237/221 ,  H01J2237/2817

Abstract: A method for measuring a surface structure of a chip or a wafer is provided that includes obtaining an image of the surface structure of the chip, and then performing an image extraction on the image to convert the extracted image into a first circuit design file. A standard image is selected to convert into a second circuit design file, and then the standard image and at least one target in the image are compared to obtain a difference therebetween. According to the difference, at least one data of the surface structure may be made, wherein the data is selected from one of line edge roughness (LER), line width roughness (LWR), contact edge roughness (CER), critical dimension (CD), bias, 3 sigma, maximum, minimum, etc. and repeating defect.

Abstract translation: 提供了一种用于测量芯片或晶片的表面结构的方法，其包括获得芯片的表面结构的图像，然后对图像执行图像提取以将提取的图像转换为第一电路设计文件。 选择标准图像以转换为第二电路设计文件，然后比较图像中的标准图像和至少一个目标，以获得它们之间的差异。 根据差异，可以进行表面结构的至少一个数据，其中数据从线边缘粗糙度（LER），线宽粗糙度（LWR），接触边缘粗糙度（CER），临界尺寸（CD） ），偏置，3西格玛，最大值，最小值等，并重复缺陷。

公开(公告)号：US20160314237A1

公开(公告)日：2016-10-27

申请号：US14694017

申请日：2015-04-23

Applicant: MACRONIX International Co., Ltd.

Inventor： Tuung Luoh ,  I-Jen Huang ,  Ling-Wuu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: G06F17/50

CPC classification number: G01R31/2831 ,  G01R31/2653

Abstract: A method for detecting defects of wafer by wafer sort is introduced. In the method, a wafer sort testing apparatus is used to obtain a DTL or ADART result, wherein a plurality of repaired sites in a wafer is highlighted according to the DTL or ADART result. A plurality of physical locations of the repaired sites is then output. An analysis equipment is used to match the physical locations with a graphic data system (GDS) design layout coordinate of the wafer so as to generate a data correlating with defects at the repaired sites.

Abstract translation: 介绍了通过晶片排序检测晶片缺陷的方法。 在该方法中，使用晶片分类测试装置来获得DTL或ADART结果，其中晶片中的多个修复位置根据DTL或ADART结果被突出显示。 然后输出修复站点的多个物理位置。 分析设备用于将物理位置与晶片的图形数据系统（GDS）设计布局坐标进行匹配，以产生与修复位置的缺陷相关的数据。

公开(公告)号：US20160123905A1

公开(公告)日：2016-05-05

申请号：US14532773

申请日：2014-11-04

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hsiang-Chou Liao ,  Tuung Luoh ,  Ling-Wuu Yang ,  Tahone Yang ,  Kuang-Chao Chen

IPC: G01N23/203 ,  H01J37/252 ,  H01L21/66

CPC classification number: G01N23/203 ,  H01J2237/2805 ,  H01J2237/2817 ,  H01L22/12

Abstract: Disclosed embodiments are generally related to semiconductor device inspection. One such embodiment involves positioning a detector at a distance from a surface of the semiconductor device being inspected and applying an energy to the semiconductor device. In the disclosed embodiment, the detector receives back-scattered energy resulting from applying the energy to the semiconductor device and the resultant back-scattered energy is processed and analyzed to determine whether defects are beneath the surface of the semiconductor device. The magnitude of the applied energy and the distance between the detector and the surface of the semiconductor device are selected so as to allow back-scattered electrons returned from applying to be effectively received by the detector.

Abstract translation: 公开的实施例通常涉及半导体器件检查。 一个这样的实施例涉及将检测器定位在距待检查的半导体器件的表面一定距离处，并向半导体器件施加能量。 在所公开的实施例中，检测器接收由向半导体器件施加能量所产生的反向散射能量，并且对所得到的反向散射能量进行处理和分析，以确定缺陷是否在半导体器件的表面之下。 选择所施加的能量的大小以及检测器与半导体器件的表面之间的距离，以便允许从施加返回的反向散射电子被检测器有效地接收。

公开(公告)号：US20150323583A1

公开(公告)日：2015-11-12

申请号：US14275437

申请日：2014-05-12

Applicant: MACRONIX International Co., Ltd.

Inventor： Hsiang-Chou Liao ,  Tuung Luoh ,  Ling-Wuu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: G01R31/04 ,  G01R31/305 ,  H01J37/28 ,  H01J37/22 ,  H01J37/244

CPC classification number: G01R31/04 ,  G01R31/305 ,  H01J37/222 ,  H01J37/244 ,  H01J37/28 ,  H01J2237/049 ,  H01J2237/063 ,  H01J2237/221 ,  H01J2237/24592 ,  H01J2237/2594 ,  H01J2237/28 ,  H01J2237/2817 ,  H01L22/12 ,  H01L22/14

Abstract: A method for detecting an electrical defect of contact/via plugs is provided. In the method, the contact/via plugs are monitored by an electron-beam (E-Beam) inspection tool to capture an image with a VC (voltage contrast) difference, and then an image extraction is performed on the image with the VC difference, wherein the image extraction is based on Target gray level/back ground gray level. The extracted image is contrasted with a layout design base to obtain a blind contact or Quasi-blind issue of contact/via plugs. A grayscale value of the VC difference having the blind contact or Quasi-blind issue is compared with a determined range of grayscale value to determine whether the VC difference is abnormal.

Abstract translation: 提供一种用于检测接触/通孔的电气缺陷的方法。 在该方法中，通过电子束（E-Beam）检查工具来监视接触/通孔塞以捕获具有VC（电压对比度）差异的图像，然后对具有VC差异的图像执行图像提取 ，其中所述图像提取基于目标灰度/背景灰度级。 提取的图像与布局设计基础形成对照，以获得接触/通孔插头的盲接或准盲问题。 将具有盲接或准盲问题的VC差的灰阶值与确定的灰度值范围进行比较，以确定VC差异是否异常。