Invention Application
- Patent Title: LAYOUT STRUCTURE FOR ELECTROSTATIC DISCHARGE PROTECTION
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Application No.: US14860788Application Date: 2015-09-22
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Publication No.: US20170084604A1Publication Date: 2017-03-23
- Inventor: Pei-Shan Tseng , Yu-Cheng Liao , Ping-Chen Chang , Tien-Hao Tang , Kuan-Cheng Su
- Applicant: UNITED MICROELECTRONICS CORP.
- Main IPC: H01L27/02
- IPC: H01L27/02

Abstract:
A layout structure is provided. The layout structure includes a substrate, a gate conductive layer, a first doped region having a first conductivity, a second doped region having the first conductivity, and a third doped region having a second conductivity. The gate conductive layer is formed on the substrate. The first doped region the second doped region are formed in the substrate and located at two sides of the gate conductive layer. The third doped region is formed in the substrate and adjacent to the second doped region. The third doped region and the second doped region form a diode. The gate conductive layer, the first doped region, and the third doped region are connected to ground, and the second doped region is connected to an input/output pad.
Public/Granted literature
- US09899369B2 Layout structure for electrostatic discharge protection Public/Granted day:2018-02-20
Information query
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