公开(公告)号：US11257807B2

公开(公告)日：2022-02-22

申请号：US17111220

申请日：2020-12-03

Applicant: United Microelectronics Corp.

Inventor： Ting-Yao Lin ,  Chun Chiang ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/74

Abstract: A semiconductor device of electrostatic discharge (ESD) protection is provided, including a deep N-type region, disposed in a substrate; a deep P-type region, disposed in the substrate; a first P-type well, disposed in the deep N-type region; a first N-type well, abutting to the first P-type well, disposed in the deep N-type region. Further, a second P-type well abutting to the first N-type well is disposed in the deep P-type region. A second N-type well abutting to the second P-type well is disposed in the deep P-type region. A side N-type well is disposed in the deep N-type region at an outer side of the first P-type well. A side P-type well is disposed in the deep P-type region at an outer side of the second N-type well.

公开(公告)号：US20190229531A1

公开(公告)日：2019-07-25

申请号：US15878421

申请日：2018-01-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Liao ,  Ting-Yao Lin ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H02H9/04 ,  H02H1/00 ,  H01L27/02

Abstract: An electrostatic discharge (ESD) protection circuit has a first power node, a second power node, an ESD detect circuit, an ESD device and a voltage controlled switch. The ESD detect circuit is coupled between the first power node and the second power node for detecting an ESD current to output a control signal at a output terminal of the ESD detect circuit. The ESD device is coupled between the first power node and the second power node for leaking the ESD current. The voltage controlled switch is used to couple a body of the ESD device to the second power node according to at least a voltage level of the control signal.

公开(公告)号：US09748222B2

公开(公告)日：2017-08-29

申请号：US15144836

申请日：2016-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Chun Chen ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L27/12 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L27/0266 ,  H01L27/0248 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/7851

Abstract: A fin type ESD protection device includes at least one first fin, at least one second fin, and at least one gate structure. The first fin is disposed on a semiconductor substrate, and a source contact contacts the first fin. The second fin is disposed on the semiconductor substrate, and a drain contact contacts the second fin. The first fin and the second fin extend in a first direction respectively, and the first fin is separated from the second fin. The gate structure is disposed between the source contact and the drain contact. The first fin is separated from the drain contact, and the second fin is separated from the source contact.

公开(公告)号：US09331064B2

公开(公告)日：2016-05-03

申请号：US14742723

申请日：2015-06-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Tzu Wang ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L21/70 ,  H01L27/02 ,  H01L29/861 ,  H01L21/76 ,  H01L29/78 ,  H01L27/06 ,  H01L29/06 ,  H01L21/22 ,  H01L21/265 ,  H01L21/306 ,  H01L29/66 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/76 ,  H01L21/76224 ,  H01L27/0629 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/785 ,  H01L29/861

Abstract: A fin diode structure includes a doped well formed in a substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well isolated from ins of first conductivity type by STIs, at least one doped region of first conductivity type in the substrate between the fins of first conductivity type, the STIs and the doped well and connecting with the fins of first conductivity type, and at least one doped region of second conductivity type in the substrate between the fins of second conductivity type, the STIs and the doped well and connecting with the fins of second conductivity type. The doping concentration of the fins of first conductivity type is greater than that of the doped region of first conductivity type whose doping concentration is greater than that of the doped well of first conductivity type.

Abstract translation: 翅片二极管结构包括在衬底中形成的掺杂阱，第一导电类型的多个鳍和第二导电类型的多个翅片，其通过STI从与第一导电类型的绝缘体隔离的掺杂阱突出，至少一个掺杂区域 第一导电类型的翅片之间的衬底中的第一导电类型，STI和掺杂阱并且与第一导电类型的鳍连接并且在第二导电类型的鳍之间的衬底中的至少一个第二导电类型的掺杂区域 类型，STI和掺杂阱，并与第二导电类型的鳍连接。 第一导电类型的散热片的掺杂浓度大于其掺杂浓度大于第一导电类型的掺杂阱的第一导电类型的掺杂区域的掺杂浓度。

公开(公告)号：US10978442B2

公开(公告)日：2021-04-13

申请号：US16446599

申请日：2019-06-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ying-Wei Tseng ,  Chun Chiang ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H01L27/02

Abstract: An electrostatic discharge (ESD) protection device and a method thereof are presented. A well is disposed in a substrate. A gate is disposed on the well. A source region and a drain region are located in the well and at two opposite sides of the gate respectively. A first doped region is located in the drain region, wherein the first doped region is electrically connected to the drain region. A second doped region is located in the source region, wherein the second doped region is electrically connected to the source region. A third doped region is located in the well and at a side of the drain region opposite to the gate. A fourth doped region is located in the well and at a side of the source region opposite to the gate, wherein the fourth doped region is electrically connected to the third doped region.

公开(公告)号：US10008492B2

公开(公告)日：2018-06-26

申请号：US15353348

申请日：2016-11-16

Applicant: United Microelectronics Corp.

Inventor： Chung-Yu Huang ,  Ping-Chen Chang ,  Hou-Jen Chiu

IPC: H01L29/06 ,  H01L27/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L27/027 ,  H01L29/0692 ,  H01L29/7835

Abstract: An electrostatic discharge (ESD) device includes a gate structure, disposed on a substrate. A drain doped region of a first conductive type is in the substrate, adjacent to a first side of the gate structure, wherein the drain doped region has a first impurity concentration. A first doped region of the first conductive type is disposed within the drain doped region and being at least distant from the gate structure by a distance. The first doped region has a second impurity concentration lower than the first impurity concentration.

公开(公告)号：US09368484B1

公开(公告)日：2016-06-14

申请号：US14723482

申请日：2015-05-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Chun Chen ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0266 ,  H01L27/0248 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/7851

Abstract: A fin type ESD protection device includes at least one first fin, at least one second fin, and at least one gate structure. The first fin is disposed on a semiconductor substrate, and a source contact contacts the first fin. The second fin is disposed on the semiconductor substrate, and a drain contact contacts the second fin. The first fin and the second fin extend in a first direction respectively, and the first fin is separated from the second fin. The gate structure is disposed between the source contact and the drain contact. The first fin is separated from the drain contact, and the second fin is separated from the source contact.

Abstract translation: 翅片型ESD保护装置包括至少一个第一鳍片，至少一个第二鳍片和至少一个栅极结构。 第一翅片设置在半导体衬底上，源极触点接触第一鳍片。 第二鳍片设置在半导体衬底上，漏极接触件接触第二鳍片。 第一鳍片和第二鳍片分别在第一方向上延伸，并且第一鳍片与第二鳍片分离。 栅极结构设置在源极触点和漏极触点之间。 第一鳍片与漏极接触部分开，第二鳍片与源极接触部分离开。

公开(公告)号：US20150287838A1

公开(公告)日：2015-10-08

申请号：US14742723

申请日：2015-06-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Tzu Wang ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L29/861 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/76 ,  H01L21/76224 ,  H01L27/0629 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/785 ,  H01L29/861

Abstract: A fin diode structure includes a doped well formed in a substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well isolated from ins of first conductivity type by STIs, at least one doped region of first conductivity type in the substrate between the fins of first conductivity type, the STIs and the doped well and connecting with the fins of first conductivity type, and at least one doped region of second conductivity type in the substrate between the fins of second conductivity type, the STIs and the doped well and connecting with the fins of second conductivity type. The doping concentration of the fins of first conductivity type is greater than that of the doped region of first conductivity type whose doping concentration is greater than that of the doped well of first conductivity type.

Abstract translation: 翅片二极管结构包括在衬底中形成的掺杂阱，第一导电类型的多个鳍和第二导电类型的多个翅片，其通过STI从与第一导电类型的绝缘体隔离的掺杂阱突出，至少一个掺杂区域 第一导电类型的翅片之间的衬底中的第一导电类型，STI和掺杂阱并且与第一导电类型的鳍连接并且在第二导电类型的鳍之间的衬底中的至少一个第二导电类型的掺杂区域 类型，STI和掺杂阱，并与第二导电类型的鳍连接。 第一导电类型的散热片的掺杂浓度大于其掺杂浓度大于第一导电类型的掺杂阱的第一导电类型的掺杂区域的掺杂浓度。

公开(公告)号：US20210091069A1

公开(公告)日：2021-03-25

申请号：US17111220

申请日：2020-12-03

Applicant: United Microelectronics Corp.

Inventor： Ting-Yao Lin ,  Chun Chiang ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/74

Abstract: A semiconductor device of electrostatic discharge (ESD) protection is provided, including a deep N-type region, disposed in a substrate; a deep P-type region, disposed in the substrate; a first P-type well, disposed in the deep N-type region; a first N-type well, abutting to the first P-type well, disposed in the deep N-type region. Further, a second P-type well abutting to the first N-type well is disposed in the deep P-type region. A second N-type well abutting to the second P-type well is disposed in the deep P-type region. A side N-type well is disposed in the deep N-type region at an outer side of the first P-type well. A side P-type well is disposed in the deep P-type region at an outer side of the second N-type well.

公开(公告)号：US20200343238A1

公开(公告)日：2020-10-29

申请号：US16394967

申请日：2019-04-25

Applicant: United Microelectronics Corp.

Inventor： Ting-Yao Lin ,  Chun Chiang ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/66

Abstract: A semiconductor device of ESD protection includes a first P-type well in a substrate to receive a protected terminal and a first N-type well abutting the first P-type well in the substrate. A second P-type well abutting the first N-type well is in the substrate. A second N-type well abutting the second P-type well is in the substrate. A detective circuit device is formed on a surface of the substrate, having an input terminal to receive the protected terminal and an output terminal to provide a trigger voltage to the first N-type well. A first route structure is in the substrate, on a sidewall and a bottom of the first P-type well to connect to a bottom of the first N-type well. A second route structure is in the substrate, on sidewall and bottom of the second N-type well, to connect to a bottom of the second P-type well.