公开(公告)号：US20170084604A1

公开(公告)日：2017-03-23

申请号：US14860788

申请日：2015-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pei-Shan Tseng ,  Yu-Cheng Liao ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02

CPC classification number: H01L27/0266 ,  H01L27/0207 ,  H01L27/0255 ,  H01L27/1203 ,  H01L28/00

Abstract: A layout structure is provided. The layout structure includes a substrate, a gate conductive layer, a first doped region having a first conductivity, a second doped region having the first conductivity, and a third doped region having a second conductivity. The gate conductive layer is formed on the substrate. The first doped region the second doped region are formed in the substrate and located at two sides of the gate conductive layer. The third doped region is formed in the substrate and adjacent to the second doped region. The third doped region and the second doped region form a diode. The gate conductive layer, the first doped region, and the third doped region are connected to ground, and the second doped region is connected to an input/output pad.

公开(公告)号：US20150054132A1

公开(公告)日：2015-02-26

申请号：US13974939

申请日：2013-08-23

Applicant: United Microelectronics Corp.

Inventor： Chang-Tzu Wang ,  Pei-Shan Tseng ,  Tien-Hao Tang

IPC: H01L29/73 ,  H01L29/66

CPC classification number: H01L29/735 ,  H01L27/0259 ,  H01L29/0821 ,  H01L29/6625 ,  H01L29/861

Abstract: Provided is a lateral BJT including a substrate, a well region, an area, at least one lightly doped region, a first doped region, and a second doped region. The substrate is of a first conductivity type. The well region is of a second conductivity type and is in the substrate. The area is in the well region. The at least one lightly doped region is in the well region below the area. The first doped region and the second doped region are of the first conductivity type and are in the well region on both sides of the area. The first doped region is connected to a cathode. The second doped region is connected to an anode, wherein the doping concentration of the at least one lightly doped region is lower than that of each of the first doped region, the second doped region, and the well region.

Abstract translation: 提供了包括衬底，阱区，区域，至少一个轻掺杂区域，第一掺杂区域和第二掺杂区域的横向BJT。 衬底是第一导电类型。 阱区是第二导电类型并且在衬底中。 该地区在该地区。 该至少一个轻掺杂区域位于该区域下方的阱区域中。 第一掺杂区域和第二掺杂区域是第一导电类型并且在该区域两侧的阱区域中。 第一掺杂区域连接到阴极。 第二掺杂区域连接到阳极，其中至少一个轻掺杂区域的掺杂浓度低于第一掺杂区域，第二掺杂区域和阱区域中的每一个的掺杂浓度。

公开(公告)号：US08981521B1

公开(公告)日：2015-03-17

申请号：US13974939

申请日：2013-08-23

Applicant: United Microelectronics Corp.

Inventor： Chang-Tzu Wang ,  Pei-Shan Tseng ,  Tien-Hao Tang

IPC: H01L29/735 ,  H01L29/73 ,  H01L29/66

CPC classification number: H01L29/735 ,  H01L27/0259 ,  H01L29/0821 ,  H01L29/6625 ,  H01L29/861

Abstract: Provided is a lateral BJT including a substrate, a well region, an area, at least one lightly doped region, a first doped region, and a second doped region. The substrate is of a first conductivity type. The well region is of a second conductivity type and is in the substrate. The area is in the well region. The at least one lightly doped region is in the well region below the area. The first doped region and the second doped region are of the first conductivity type and are in the well region on both sides of the area. The first doped region is connected to a cathode. The second doped region is connected to an anode, wherein the doping concentration of the at least one lightly doped region is lower than that of each of the first doped region, the second doped region, and the well region.

Abstract translation: 提供了包括衬底，阱区，区域，至少一个轻掺杂区域，第一掺杂区域和第二掺杂区域的横向BJT。 衬底是第一导电类型。 阱区是第二导电类型并且在衬底中。 该地区在该地区。 至少一个轻掺杂区域位于该区域下方的阱区域中。 第一掺杂区域和第二掺杂区域是第一导电类型并且在该区域两侧的阱区域中。 第一掺杂区域连接到阴极。 第二掺杂区域连接到阳极，其中至少一个轻掺杂区域的掺杂浓度低于第一掺杂区域，第二掺杂区域和阱区域中的每一个的掺杂浓度。

公开(公告)号：US09899369B2

公开(公告)日：2018-02-20

申请号：US14860788

申请日：2015-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pei-Shan Tseng ,  Yu-Cheng Liao ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L27/12

CPC classification number: H01L27/0266 ,  H01L27/0207 ,  H01L27/0255 ,  H01L27/1203 ,  H01L28/00

Abstract: A layout structure is provided. The layout structure includes a substrate, a gate conductive layer, a first doped region having a first conductivity, a second doped region having the first conductivity, and a third doped region having a second conductivity. The gate conductive layer is formed on the substrate. The first doped region the second doped region are formed in the substrate and located at two sides of the gate conductive layer. The third doped region is formed in the substrate and adjacent to the second doped region. The third doped region and the second doped region form a diode. The gate conductive layer, the first doped region, and the third doped region are connected to ground, and the second doped region is connected to an input/output pad.