Invention Application
- Patent Title: METHOD FOR PRODUCING A SEMICONDUCTOR POWER DEVICE (DMOS) INCLUDING GATE ELECTRODE FORMED OVER A GATE INSULATION FILM HAVING SiO2 PORTIONS AND A HIGH-K PORTION THEREBETWEEN
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Application No.: US15261830Application Date: 2016-09-09
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Publication No.: US20170092743A1Publication Date: 2017-03-30
- Inventor: Keiji OKUMURA , Mineo MIURA , Yuki NAKANO , Noriaki KAWAMOTO , Hidetoshi ABE
- Applicant: ROHM CO., LTD.
- Applicant Address: JP Kyoto
- Assignee: ROHM CO., LTD.
- Current Assignee: ROHM CO., LTD.
- Current Assignee Address: JP Kyoto
- Priority: JP2010-078280 20100330
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/78 ; H01L21/311 ; H01L29/423 ; H01L21/02
Abstract:
A method for producing a semiconductor power device, includes forming a gate trench from a surface of a semiconductor layer toward an inside thereof. A first insulation film is formed on an inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.
Public/Granted literature
Information query
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