Invention Application
- Patent Title: REVERSE SELF ALIGNED DOUBLE PATTERNING PROCESS FOR BACK END OF LINE FABRICATION OF A SEMICONDUCTOR DEVICE
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Application No.: US15390405Application Date: 2016-12-23
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Publication No.: US20170110364A1Publication Date: 2017-04-20
- Inventor: Stanley Seungchul Song , Choh Fei Yeap , Zhongze Wang , John Jianhong Zhu
- Applicant: QUALCOMM Incorporated
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/033 ; H01L23/66 ; H01L23/522 ; H01L23/528
Abstract:
In a particular embodiment, a method includes forming a second hardmask layer adjacent to a first sidewall structure and adjacent to a mandrel of a semiconductor device. A top portion of the mandrel is exposed prior to formation of the second hardmask layer. The method further includes removing the first sidewall structure to expose a first portion of a first hardmask layer. The method also includes etching the first portion of the first hardmask layer to expose a second portion of a dielectric material. The method also includes etching the second portion of the dielectric material to form a first trench. The method also includes forming a first metal structure within the first trench.
Public/Granted literature
- US09941154B2 Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device Public/Granted day:2018-04-10
Information query
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