公开(公告)号：US20180301447A1

公开(公告)日：2018-10-18

申请号：US15487664

申请日：2017-04-14

申请人： QUALCOMM Incorporated

发明人： John Jianhong Zhu ,  Da Yang ,  Jeffrey Junhao Xu

IPC分类号： H01L27/088 ,  H01L23/528 ,  H01L27/02 ,  H01L29/06 ,  H01L21/8234

摘要： Metal-oxide semiconductor (MOS) standard cells employing electrically coupled source regions and supply rails to relax source-drain tip-to-tip spacing between adjacent MOS standard cells are disclosed. In one aspect, a MOS standard cell includes supply rails disposed in a first metal layer and along respective axes in an X-axis direction. The MOS standard cell includes metal lines disposed in the first metal layer and along respective axes in the X-axis direction. The MOS standard cell includes a source region formed in a semiconductor substrate beneath the first metal layer and adjacent to a plane in an X-Z-axis direction disposed between a supply rail and the source region. The source region is electrically coupled to the corresponding supply rail. Forming the source region in this manner allows the MOS standard cell to be disposed adjacent to other MOS standard cells while achieving the minimum required source-drain tip-to-tip spacing.

公开(公告)号：US10079293B2

公开(公告)日：2018-09-18

申请号：US15839050

申请日：2017-12-12

申请人： QUALCOMM Incorporated

发明人： Jeffrey Junhao Xu ,  Kern Rim ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  Vladimir Machkaoutsan ,  Da Yang ,  Choh Fei Yeap

IPC分类号： H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/6681 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： A method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap.

公开(公告)号：US10043796B2

公开(公告)日：2018-08-07

申请号：US15097142

申请日：2016-04-12

申请人： QUALCOMM Incorporated

发明人： Vladimir Machkaoutsan ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  John Jianhong Zhu ,  Junjing Bao ,  Jeffrey Junhao Xu ,  Da Yang ,  Matthew Michael Nowak ,  Choh Fei Yeap

IPC分类号： H01L29/06 ,  H01L27/088 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/423 ,  H01L27/06

摘要： A device includes a substrate, a first nanowire field effect transistor (FET), and a second nanowire FET positioned between the substrate and the first nanowire FET. The device also includes a first nanowire electrically coupled to the first nanowire FET and to the second nanowire FET.

公开(公告)号：US20170221884A1

公开(公告)日：2017-08-03

申请号：US15097142

申请日：2016-04-12

申请人： QUALCOMM Incorporated

发明人： Vladimir Machkaoutsan ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  John Jianhong Zhu ,  Junjing Bao ,  Jeffrey Junhao Xu ,  Da Yang ,  Matthew Michael Nowak ,  Choh Fei Yeap

IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/02

CPC分类号： H01L27/088 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/0207 ,  H01L27/0688 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0676 ,  H01L29/42392

摘要： A device includes a substrate, a first nanowire field effect transistor (FET), and a second nanowire FET positioned between the substrate and the first nanowire FET. The device also includes a first nanowire electrically coupled to the first nanowire FET and to the second nanowire FET.

公开(公告)号：US09564361B2

公开(公告)日：2017-02-07

申请号：US14026893

申请日：2013-09-13

申请人： QUALCOMM Incorporated

发明人： Stanley Seungchul Song ,  Choh Fei Yeap ,  Zhongze Wang ,  John Jianhong Zhu

IPC分类号： H01L21/768 ,  G06F17/50 ,  H01L23/522 ,  H01L21/033 ,  H01L21/311

CPC分类号： H01L21/76816 ,  G06F17/5068 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/66 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a particular embodiment, a method includes forming a second hardmask layer adjacent to a first sidewall structure and adjacent to a mandrel of a semiconductor device. A top portion of the mandrel is exposed prior to formation of the second hardmask layer. The method further includes removing the first sidewall structure to expose a first portion of a first hardmask layer. The method also includes etching the first portion of the first hardmask layer to expose a second portion of a dielectric material. The method also includes etching the second portion of the dielectric material to form a first trench. The method also includes forming a first metal structure within the first trench.

摘要翻译： 在特定实施例中，一种方法包括形成与第一侧壁结构相邻并与半导体器件的心轴相邻的第二硬掩模层。 心轴的顶部在形成第二硬掩模层之前被暴露。 该方法还包括去除第一侧壁结构以暴露第一硬掩模层的第一部分。 该方法还包括蚀刻第一硬掩模层的第一部分以暴露电介质材料的第二部分。 该方法还包括蚀刻介电材料的第二部分以形成第一沟槽。 该方法还包括在第一沟槽内形成第一金属结构。

公开(公告)号：US09379058B2

公开(公告)日：2016-06-28

申请号：US14274184

申请日：2014-05-09

申请人： QUALCOMM Incorporated

发明人： Stanley Seungchul Song ,  Zhongze Wang ,  Ohsang Kwon ,  Kern Rim ,  John Jianhong Zhu ,  Xiangdong Chen ,  Foua Vang ,  Raymond George Stephany ,  Choh Fei Yeap

IPC分类号： H01L29/423 ,  H01L29/417 ,  H01L23/528 ,  H01L23/522 ,  H01L27/088 ,  H01L21/768 ,  H01L27/118

CPC分类号： H01L23/5283 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/088 ,  H01L29/41775 ,  H01L29/42312 ,  H01L2027/11866 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a gate and a first active contact adjacent to the gate. Such a device further includes a first stacked contact electrically coupled to the first active contact, including a first isolation layer on sidewalls electrically isolating the first stacked contact from the gate. The device also includes a first via electrically coupled to the gate and landing on the first stacked contact. The first via electrically couples the first stacked contact and the first active contact to the gate to ground the gate.

摘要翻译： 半导体器件包括栅极和邻近栅极的第一有源触点。 这种器件还包括电耦合到第一有源触点的第一堆叠触点，包括在侧壁上电隔离第一堆叠触头与栅极的第一隔离层。 该装置还包括电连接到门的第一通孔和第一堆叠接触件上的着陆。 第一通孔将第一堆叠触点和第一有源触点电耦合到栅极以将栅极接地。

公开(公告)号：US20160172456A1

公开(公告)日：2016-06-16

申请号：US14567925

申请日：2014-12-11

申请人： QUALCOMM Incorporated

发明人： Xia Li ,  John Jianhong Zhu ,  Jeffrey Junhao Xu ,  Bin Yang ,  Jun Yuan ,  Yu Lu

IPC分类号： H01L29/417 ,  H01L21/283

CPC分类号： H01L29/41775 ,  H01L21/76841 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor device includes a transistor having a metal gate, a source, and a drain. The semiconductor device also includes a high resistance metal etch-stop layer positioned above the metal gate of the transistor. The semiconductor device also includes a metal layer formed on the high resistance metal etch-stop layer. The metal layer is positioned above at least one of the source of the transistor or the drain of the transistor.

摘要翻译： 半导体器件包括具有金属栅极，源极和漏极的晶体管。 半导体器件还包括位于晶体管的金属栅极上方的高电阻金属蚀刻停止层。 半导体器件还包括形成在高电阻金属蚀刻停止层上的金属层。 金属层位于晶体管的源极或晶体管的漏极中的至少一个的上方。

公开(公告)号：US20160126144A1

公开(公告)日：2016-05-05

申请号：US14991882

申请日：2016-01-08

申请人： QUALCOMM Incorporated

发明人： Jeffrey Junhao Xu ,  Kern Rim ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Choh Fei Yeap

IPC分类号： H01L21/8238 ,  H01L21/285 ,  H01L21/324 ,  H01L29/66

CPC分类号： H01L21/823814 ,  C23C14/24 ,  C23C14/54 ,  C23C16/46 ,  C23C16/52 ,  H01L21/285 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/324 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/66568

摘要： A method includes forming a first metal layer on source/drain regions of an n-type metal-oxide-semiconductor (NMOS) device and on source/drain regions of a p-type MOS (PMOS) device by chemical vapor deposition (CVD) or non-energetic physical vapor deposition (PVD). The method further includes selectively performing a rapid thermal anneal (RTA) process on the first metal layer after forming the first metal layer.

公开(公告)号：US20190296126A1

公开(公告)日：2019-09-26

申请号：US15927343

申请日：2018-03-21

申请人： QUALCOMM Incorporated

发明人： Stanley Seungchul Song ,  Kern Rim ,  Da Yang ,  John Jianhong Zhu

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L23/535 ,  H01L27/088 ,  H01L27/02 ,  H01L21/768 ,  H01L29/417

摘要： Systems and methods for dummy gate tie-offs in a self-aligned gate contact (SAGC) cell are disclosed. In particular, exemplary aspects contemplate a two-part etching process to remove hardmasks formed from different materials from adjacent elements. A metal fill material may then be used to tie off the adjacent elements. The use of the two-part etching process allows SAGC techniques to be used for a first portion of a cell while still providing a technique to allow a tie-off in a second portion of the cell. The tie-off may be used with a dummy gate to provide isolation between cells.

公开(公告)号：US10163792B2

公开(公告)日：2018-12-25

申请号：US14444104

申请日：2014-07-28

申请人： QUALCOMM Incorporated

发明人： John Jianhong Zhu ,  Jeffrey Junhao Xu ,  Choh Fei Yeap ,  Stanley Seungchul Song ,  Kern Rim

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L21/321 ,  H01L23/522 ,  H01L23/532

摘要： An apparatus includes a first interconnect and a first barrier structure. The first barrier structure is in contact with a dielectric material. The apparatus further includes a first protective structure in contact with the first barrier structure and an etch stop layer. An airgap is defined at least in part by the first protective structure and the etch stop layer.