Methods and systems for improved matching of on-chip capacitors may comprise a semiconductor die with an on-chip capacitor comprising one or more metal layers. The on-chip capacitor may comprise interdigitated electrically coupled metal fingers. The electrically coupled metal fingers may be arranged symmetrically in the semiconductor die to compensate for non-uniformities in the one or more metal layers. The metal fingers may be arranged with radial symmetry. Metal fingers in a first metal layer may be electrically coupled to metal fingers in a second metal layer. An orientation of metal fingers may be alternated when coupling metal fingers in a plurality of metal layers. The metal fingers may be coupled at the center or the outer edge of the on-chip capacitor. The on-chip capacitor may be configured in a plurality of symmetric sections wherein a boundary between each of the plurality of sections is configured in a zig-zag pattern.