Invention Application
- Patent Title: JOINT CROSSTALK-AVOIDANCE AND ERROR-CORRECTION CODING FOR PARALLEL DATA BUSSES
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Application No.: US14958883Application Date: 2015-12-03
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Publication No.: US20170163375A1Publication Date: 2017-06-08
- Inventor: Urs Niesen , Shrinivas Kudekar
- Applicant: QUALCOMM Incorporated
- Main IPC: H04L1/00
- IPC: H04L1/00 ; G06F13/42 ; H04L1/08

Abstract:
System, methods, and apparatus are described that facilitate transmission/reception of data over a multi-line parallel bus. In an example, the apparatus transmits data bits over a parallel bus includes determining from a prior bus state, a plurality of free wires in the bus for a current bus state, where each free wire satisfies a crosstalk-avoidance constraint in the current bus state for all values of a bit transmitted on the free wire. The apparatus may encode a plurality of data bits using a crosstalk avoidance encoder to obtain a CAC-encoded word, compute an error detection or correction code for the CAC-encoded word, assign bits of the error detection or correction code to the plurality of free wires for transmission during the current bus state, and assign the CAC-encoded word to unassigned wires of the bus for transmission during the current bus state.
Public/Granted literature
- US09654251B1 Joint crosstalk-avoidance and error-correction coding for parallel data busses Public/Granted day:2017-05-16
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