Invention Application
- Patent Title: CARRIER-FREE SEMICONDUCTOR PACKAGE AND FABRICATION METHOD
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Application No.: US15467198Application Date: 2017-03-23
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Publication No.: US20170200671A1Publication Date: 2017-07-13
- Inventor: Yueh-Ying Tsai , Fu-Di Tang , Chien-Ping Huang , Chun-Chi Ke
- Applicant: Siliconware Precision Industries Co., Ltd.
- Priority: TW99118110 20100604; TW99133823 20101005
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L21/56 ; H01L23/31 ; H01L23/00 ; H01L21/48 ; H01L21/683

Abstract:
A method for fabricating a carrier-free semiconductor package includes: half-etching a metal carrier to form a plurality of recess grooves and a plurality of metal studs each serving in position as a solder pad or a die pad; filing each of the recess grooves with a first encapsulant; forming on the metal studs an antioxidant layer such as a silver plating layer or an organic solderable protection layer; and performing die-bonding, wire-bonding and molding processes respectively to form a second encapsulant encapsulating the chip. The recess grooves are filled with the first encapsulant to enhance the adhesion between the first encapsulant and the metal carrier, thereby solving the conventional problem of having a weak and pliable copper plate and avoiding transportation difficulty. The invention eliminates the use of costly metals as an etching resist layer to reduce fabrication cost, and further allows conductive traces to be flexibly disposed on the metal carrier to enhance electrical connection quality.
Public/Granted literature
- US10566271B2 Carrier-free semiconductor package and fabrication method Public/Granted day:2020-02-18
Information query
IPC分类: