公开(公告)号：US20170200671A1

公开(公告)日：2017-07-13

申请号：US15467198

申请日：2017-03-23

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yueh-Ying Tsai ,  Fu-Di Tang ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683

Abstract: A method for fabricating a carrier-free semiconductor package includes: half-etching a metal carrier to form a plurality of recess grooves and a plurality of metal studs each serving in position as a solder pad or a die pad; filing each of the recess grooves with a first encapsulant; forming on the metal studs an antioxidant layer such as a silver plating layer or an organic solderable protection layer; and performing die-bonding, wire-bonding and molding processes respectively to form a second encapsulant encapsulating the chip. The recess grooves are filled with the first encapsulant to enhance the adhesion between the first encapsulant and the metal carrier, thereby solving the conventional problem of having a weak and pliable copper plate and avoiding transportation difficulty. The invention eliminates the use of costly metals as an etching resist layer to reduce fabrication cost, and further allows conductive traces to be flexibly disposed on the metal carrier to enhance electrical connection quality.

公开(公告)号：US09177837B2

公开(公告)日：2015-11-03

申请号：US14221667

申请日：2014-03-21

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Pang-Chun Lin ,  Chun-Yuan Li ,  Fu-Di Tang ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/85001 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability.

Abstract translation: 具有电连接结构的半导体封装包括：具有管芯焊盘和围绕管芯焊盘的迹线的导电层; 一个芯片 接合线; 具有多个空腔的密封剂，其深度大于管芯焊盘的厚度，以及用于将管芯焊盘和其中的迹线嵌入其中的迹线，以及暴露管芯焊盘和迹线的空腔; 形成在所述空腔中的焊料掩模层，并且具有用于暴露所述迹线端部和所述管芯焊盘的一部分的多个开口; 以及形成在开口中并电连接到迹线端的焊球。 将焊料掩模层与密封剂接合，增强了焊料掩模层的粘合强度，从而延长了水分渗透路径并提高了封装的可靠性。

公开(公告)号：US09190296B2

公开(公告)日：2015-11-17

申请号：US14319321

申请日：2014-06-30

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yueh-Ying Tsai ,  Fu-Di Tang ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/3142 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/81395 ,  H01L2224/81439 ,  H01L2224/83395 ,  H01L2224/83439 ,  H01L2224/85001 ,  H01L2224/85395 ,  H01L2224/85439 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package without a chip carrier formed thereon and a fabrication method thereof. A metallic carrier is half-etched to form a plurality of grooves and metal studs corresponding to the grooves. The grooves are filled with a first encapsulant and a plurality of bonding pads are formed on the metal studs. The first encapsulant is bonded with the metal studs directly. Each of the bonding pads and one of the metal studs corresponding to the bonding pad form a T-shaped structure. Therefore, bonding force between the metal studs and the first encapsulant is enhanced such that delamination is avoided. Die mounting, wire-bonding and molding processes are performed subsequently. Since the half-etched grooves are filled with the first encapsulant, the drawback of having pliable metallic carrier that makes transportation difficult to carry out as encountered in prior techniques is overcome, and the manufacturing cost is educed by not requiring the use of costly metals as an etching resist layer.

Abstract translation: 其上形成有芯片载体的半导体封装及其制造方法。 金属载体被半蚀刻以形成对应于凹槽的多个凹槽和金属螺柱。 凹槽填充有第一密封剂，并且在金属螺柱上形成多个接合焊盘。 第一密封剂直接与金属螺栓结合。 每个接合焊盘和对应于接合焊盘的一个金属螺柱形成T形结构。 因此，金属螺柱和第一密封剂之间的结合力增强，从而避免分层。 随后进行模具安装，引线接合和成型工艺。 由于半蚀刻槽被第一密封剂填充，因此克服了使现有技术中遇到的导致难以进行运输的柔韧金属载体的缺陷，并且通过不需要使用昂贵的金属来促进制造成本 抗蚀剂层。

公开(公告)号：US20140315351A1

公开(公告)日：2014-10-23

申请号：US14319321

申请日：2014-06-30

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yueh-Ying Tsai ,  Fu-Di Tang ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC: H01L21/48 ,  H01L23/00

CPC classification number: H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/3142 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/81395 ,  H01L2224/81439 ,  H01L2224/83395 ,  H01L2224/83439 ,  H01L2224/85001 ,  H01L2224/85395 ,  H01L2224/85439 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package without a chip carrier formed thereon and a fabrication method thereof. A metallic carrier is half-etched to form a plurality of grooves and metal studs corresponding to the grooves. The grooves are filled with a first encapsulant and a plurality of bonding pads are formed on the metal studs. The first encapsulant is bonded with the metal studs directly. Each of the bonding pads and one of the metal studs corresponding to the bonding pad form a T-shaped structure. Therefore, bonding force between the metal studs and the first encapsulant is enhanced such that delamination is avoided. Die mounting, wire-bonding and molding processes are performed subsequently. Since the half-etched grooves are filled with the first encapsulant, the drawback of having pliable metallic carrier that makes transportation difficult to carry out as encountered in prior techniques is overcome, and the manufacturing cost is educed by not requiring the use of costly metals as an etching resist layer.

Abstract translation: 其上形成有芯片载体的半导体封装及其制造方法。 金属载体被半蚀刻以形成对应于凹槽的多个凹槽和金属螺柱。 凹槽填充有第一密封剂，并且在金属螺柱上形成多个接合焊盘。 第一密封剂直接与金属螺栓结合。 每个接合焊盘和对应于接合焊盘的一个金属螺柱形成T形结构。 因此，金属螺柱和第一密封剂之间的结合力增强，从而避免分层。 随后进行模具安装，引线接合和成型工艺。 由于半蚀刻槽被第一密封剂填充，因此克服了使现有技术中遇到的导致难以进行运输的柔韧金属载体的缺陷，并且通过不需要使用昂贵的金属来促进制造成本 抗蚀剂层。

公开(公告)号：US20140206146A1

公开(公告)日：2014-07-24

申请号：US14221667

申请日：2014-03-21

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Pang-Chun Lin ,  Chun-Yuan Li ,  Fu-Di Tang ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC: H01L21/56 ,  H01L21/78

CPC classification number: H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/85001 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability.

Abstract translation: 具有电连接结构的半导体封装包括：具有管芯焊盘和围绕管芯焊盘的迹线的导电层; 一个芯片 接合线; 具有多个空腔的密封剂，其深度大于管芯焊盘的厚度，以及用于将管芯焊盘和其中的迹线嵌入其中的迹线，以及暴露管芯焊盘和迹线的空腔; 形成在所述空腔中的焊料掩模层，并且具有用于暴露所述迹线端部和所述管芯焊盘的一部分的多个开口; 以及形成在开口中并电连接到迹线端的焊球。 将焊料掩模层与密封剂接合，增强了焊料掩模层的粘合强度，从而延长了水分渗透路径并提高了封装的可靠性。

公开(公告)号：US10566271B2

公开(公告)日：2020-02-18

申请号：US15467198

申请日：2017-03-23

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yueh-Ying Tsai ,  Fu-Di Tang ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L21/56

Abstract: A method for fabricating a carrier-free semiconductor package includes: half-etching a metal carrier to form a plurality of recess grooves and a plurality of metal studs each serving in position as a solder pad or a die pad; filing each of the recess grooves with a first encapsulant; forming on the metal studs an antioxidant layer such as a silver plating layer or an organic solderable protection layer; and performing die-bonding, wire-bonding and molding processes respectively to form a second encapsulant encapsulating the chip. The recess grooves are filled with the first encapsulant to enhance the adhesion between the first encapsulant and the metal carrier, thereby solving the conventional problem of having a weak and pliable copper plate and avoiding transportation difficulty. The invention eliminates the use of costly metals as an etching resist layer to reduce fabrication cost, and further allows conductive traces to be flexibly disposed on the metal carrier to enhance electrical connection quality.

公开(公告)号：US20140162409A1

公开(公告)日：2014-06-12

申请号：US14096272

申请日：2013-12-04

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Fu-Di Tang ,  Ching-Chiuan Wei ,  Yung-Chih Lin

IPC: H01L21/56 ,  H01L23/00

CPC classification number: H01L21/561 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49582 ,  H01L23/552 ,  H01L24/89 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A Quad Flat No-Lead (QFN) semiconductor package includes a die pad; I/O connections disposed at the periphery of the die pad; a chip mounted on the die pad; bonding wires; an encapsulant for encapsulating the die pad, the I/O connections, the chip and the bonding wires while exposing the bottom surfaces of the die pad and the I/O connections; a surface layer formed on the bottoms surfaces of the die pad and the I/O connections; a dielectric layer formed on the bottom surfaces of the encapsulant and the surface layer and having openings for exposing the surface layer. The surface layer has good bonding with the dielectric layer that helps to prevent solder material in a reflow process from permeating into the die pad and prevent solder extrusion on the interface of the I/O connections and the dielectric layer, thereby increasing product yield.

Abstract translation: 四通道扁平无引线（QFN）半导体封装包括管芯焊盘; 设置在管芯焊盘周边的I / O连接; 安装在芯片焊盘上的芯片; 接合线; 用于封装芯片焊盘的密封剂，I / O连接，芯片和接合线，同时暴露管芯焊盘的底表面和I / O连接; 形成在管芯焊盘的底部表面上的表面层和I / O连接; 形成在密封剂和表面层的底表面上并具有用于暴露表面层的开口的电介质层。 表面层与电介质层具有良好的结合，有助于防止回流工艺中的焊料渗透到芯片焊盘中并防止焊料挤出在I / O连接和电介质层的界面上，从而提高产品产量。

公开(公告)号：US11289409B2

公开(公告)日：2022-03-29

申请号：US16734617

申请日：2020-01-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yueh-Ying Tsai ,  Fu-Di Tang ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/495 ,  H01L23/31 ,  H01L23/00

Abstract: A method for fabricating a carrier-free semiconductor package includes: half-etching a metal carrier to form a plurality of recess grooves and a plurality of metal studs each serving in position as a solder pad or a die pad; filing each of the recess grooves with a first encapsulant; forming on the metal studs an antioxidant layer such as a silver plating layer or an organic solderable protection layer; and performing die-bonding, wire-bonding and molding processes respectively to form a second encapsulant encapsulating the chip. The recess grooves are filled with the first encapsulant to enhance the adhesion between the first encapsulant and the metal carrier, thereby solving the conventional problem of having a weak and pliable copper plate and avoiding transportation difficulty. The invention eliminates the use of costly metals as an etching resist layer to reduce fabrication cost, and further allows conductive traces to be flexibly disposed on the metal carrier to enhance electrical connection quality.

公开(公告)号：US08835225B2

公开(公告)日：2014-09-16

申请号：US14096272

申请日：2013-12-04

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Fu-Di Tang ,  Ching-Chiuan Wei ,  Yung-Chih Lin

IPC: H01L21/56

CPC classification number: H01L21/561 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49582 ,  H01L23/552 ,  H01L24/89 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A Quad Flat No-Lead (QFN) semiconductor package includes a die pad; I/O connections disposed at the periphery of the die pad; a chip mounted on the die pad; bonding wires; an encapsulant for encapsulating the die pad, the I/O connections, the chip and the bonding wires while exposing the bottom surfaces of the die pad and the I/O connections; a surface layer formed on the bottoms surfaces of the die pad and the I/O connections; a dielectric layer formed on the bottom surfaces of the encapsulant and the surface layer and having openings for exposing the surface layer. The surface layer has good bonding with the dielectric layer that helps to prevent solder material in a reflow process from permeating into the die pad and prevent solder extrusion on the interface of the I/O connections and the dielectric layer, thereby increasing product yield.

Abstract translation: 四通道扁平无引线（QFN）半导体封装包括管芯焊盘; 设置在管芯焊盘周边的I / O连接; 安装在芯片焊盘上的芯片; 接合线; 用于封装芯片焊盘的密封剂，I / O连接，芯片和接合线，同时暴露管芯焊盘的底表面和I / O连接; 形成在管芯焊盘的底部表面上的表面层和I / O连接; 形成在密封剂和表面层的底表面上并具有用于暴露表面层的开口的电介质层。 表面层与电介质层具有良好的结合，有助于防止回流工艺中的焊料渗透到芯片焊盘中并防止焊料挤出在I / O连接和电介质层的界面上，从而提高产品产量。

公开(公告)号：US08716861B2

公开(公告)日：2014-05-06

申请号：US13779077

申请日：2013-02-27

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Pang-Chun Lin ,  Chun-Yuan Li ,  Fu-Di Tang ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/85001 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability.

Abstract translation: 具有电连接结构的半导体封装包括：具有管芯焊盘和围绕管芯焊盘的迹线的导电层; 一个芯片 接合线; 具有多个空腔的密封剂，其深度大于管芯焊盘的厚度，以及用于将管芯焊盘和其中的迹线嵌入其中的迹线，以及暴露管芯焊盘和迹线的空腔; 形成在所述空腔中的焊料掩模层，并且具有用于暴露所述迹线端部和所述管芯焊盘的一部分的多个开口; 以及形成在开口中并电连接到迹线端的焊球。 将焊料掩模层与密封剂接合，增强了焊料掩模层的粘合强度，从而延长了水分渗透路径并提高了封装的可靠性。