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    Carrier-free semiconductor package and fabrication method
    1.
    发明授权
    Carrier-free semiconductor package and fabrication method 有权

    公开(公告)号：US10566271B2

    公开(公告)日：2020-02-18

    申请号：US15467198

    申请日：2017-03-23

    申请人： Siliconware Precision Industries Co., Ltd.

    发明人： Yueh-Ying Tsai ,  Fu-Di Tang ,  Chien-Ping Huang ,  Chun-Chi Ke

    IPC分类号： H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L21/56

    摘要： A method for fabricating a carrier-free semiconductor package includes: half-etching a metal carrier to form a plurality of recess grooves and a plurality of metal studs each serving in position as a solder pad or a die pad; filing each of the recess grooves with a first encapsulant; forming on the metal studs an antioxidant layer such as a silver plating layer or an organic solderable protection layer; and performing die-bonding, wire-bonding and molding processes respectively to form a second encapsulant encapsulating the chip. The recess grooves are filled with the first encapsulant to enhance the adhesion between the first encapsulant and the metal carrier, thereby solving the conventional problem of having a weak and pliable copper plate and avoiding transportation difficulty. The invention eliminates the use of costly metals as an etching resist layer to reduce fabrication cost, and further allows conductive traces to be flexibly disposed on the metal carrier to enhance electrical connection quality.

    SEMICONDUCTOR PACKAGE STRUCTURE
    8.
    发明申请
    SEMICONDUCTOR PACKAGE STRUCTURE 有权
    半导体封装结构

    公开(公告)号：US20130200508A1

    公开(公告)日：2013-08-08

    申请号：US13834787

    申请日：2013-03-15

    申请人： Siliconware Precision Industries Co., Ltd.

    发明人： Pang-Chun Lin ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

    IPC分类号： H01L23/495

    CPC分类号： H01L23/495 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/4951 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/181 ,  Y10T29/49117 ,  Y10T29/49171 ,  Y10T29/49172 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： A semiconductor package structure includes: a dielectric layer; a metal layer disposed on the dielectric layer and having a die pad and traces, the traces each including a trace body, a bond pad extending to the periphery of the die pad, and an opposite trace end; metal pillars penetrating the dielectric layer with one ends thereof connecting to the die pad and the trace ends while the other ends thereof protruding from the dielectric layer; a semiconductor chip mounted on the die pad and electrically connected to the bond pads through bonding wires; and an encapsulant covering the semiconductor chip, the bonding wires, the metal layer, and the dielectric layer. The invention is characterized by disposing traces with bond pads close to the die pad to shorten bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging encountered in prior techniques.

    摘要翻译： 半导体封装结构包括：电介质层; 设置在电介质层上并具有芯片焊盘和迹线的金属层，每个迹线包括迹线体，延伸到管芯焊盘周边的接合焊盘和相对的迹线端; 金属柱贯穿电介质层，其一端连接到管芯焊盘并且其端部从电介质层突出; 半导体芯片，安装在芯片焊盘上，并通过接合线电连接到焊盘; 以及覆盖半导体芯片，接合线，金属层和电介质层的密封剂。 本发明的特征在于，将具有接合焊盘的迹线设置在芯片焊盘附近以缩短接合线并形成从电介质层突出的金属柱，以避免在现有技术中遇到的焊料桥接。

    CARRIER-FREE SEMICONDUCTOR PACKAGE AND FABRICATION METHOD
    9.
    发明申请
    CARRIER-FREE SEMICONDUCTOR PACKAGE AND FABRICATION METHOD 审中-公开

    公开(公告)号：US20170200671A1

    公开(公告)日：2017-07-13

    申请号：US15467198

    申请日：2017-03-23

    申请人： Siliconware Precision Industries Co., Ltd.

    发明人： Yueh-Ying Tsai ,  Fu-Di Tang ,  Chien-Ping Huang ,  Chun-Chi Ke

    IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683

    摘要： A method for fabricating a carrier-free semiconductor package includes: half-etching a metal carrier to form a plurality of recess grooves and a plurality of metal studs each serving in position as a solder pad or a die pad; filing each of the recess grooves with a first encapsulant; forming on the metal studs an antioxidant layer such as a silver plating layer or an organic solderable protection layer; and performing die-bonding, wire-bonding and molding processes respectively to form a second encapsulant encapsulating the chip. The recess grooves are filled with the first encapsulant to enhance the adhesion between the first encapsulant and the metal carrier, thereby solving the conventional problem of having a weak and pliable copper plate and avoiding transportation difficulty. The invention eliminates the use of costly metals as an etching resist layer to reduce fabrication cost, and further allows conductive traces to be flexibly disposed on the metal carrier to enhance electrical connection quality.