Invention Application
- Patent Title: COMPENSATING FOR LITHOGRAPHIC LIMITATIONS IN FABRICATING SEMICONDUCTOR INTERCONNECT STRUCTURES
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Application No.: US15053818Application Date: 2016-02-25
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Publication No.: US20170250080A1Publication Date: 2017-08-31
- Inventor: Guillaume BOUCHE , Jason Eugene STEPHENS
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Main IPC: H01L21/033
- IPC: H01L21/033 ; H01L23/532 ; H01L23/522 ; H01L21/768 ; H01L23/528
Abstract:
A hard mask is formed into lines and bridges two adjacent lines using mandrels, spacers for the mandrels and a lithographic process for each bridge to create a metal line pattern in a layer of an interconnect structure with a line pitch below lithographic resolution.
Public/Granted literature
- US09779943B2 Compensating for lithographic limitations in fabricating semiconductor interconnect structures Public/Granted day:2017-10-03
Information query
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