公开(公告)号：US20170250080A1

公开(公告)日：2017-08-31

申请号：US15053818

申请日：2016-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume BOUCHE ,  Jason Eugene STEPHENS

IPC: H01L21/033 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L21/0337 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53228

Abstract: A hard mask is formed into lines and bridges two adjacent lines using mandrels, spacers for the mandrels and a lithographic process for each bridge to create a metal line pattern in a layer of an interconnect structure with a line pitch below lithographic resolution.

公开(公告)号：US20170278720A1

公开(公告)日：2017-09-28

申请号：US15077480

申请日：2016-03-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Eugene STEPHENS ,  Guillaume BOUCHE ,  Byoung Youp KIM ,  Craig Michael CHILD, JR.

IPC: H01L21/3213

CPC classification number: H01L21/32 ,  H01L21/0337 ,  H01L21/31144

Abstract: A method for forming a pattern for interconnection lines and associated continuity dielectric blocks in an integrated circuit includes providing a structure having a mandrel layer disposed over an etch mask layer, the etch mask layer being disposed over a pattern layer and the pattern layer being disposed over a dielectric stack. Patterning an array of mandrels in the mandrel layer. Selectively etching a beta trench entirely in a mandrel of the array, the beta trench overlaying a beta block mask portion of the pattern layer. Selectively etching a gamma trench entirely in the etch mask layer, the gamma trench overlaying a gamma block mask portion of the pattern layer. Selectively etching the structure to form a pattern in the pattern layer, the pattern including the gamma and beta block mask portions.

公开(公告)号：US20170309560A1

公开(公告)日：2017-10-26

申请号：US15136384

申请日：2016-04-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume BOUCHE ,  Jason Eugene STEPHENS ,  Tuhin GUHA NEOGI ,  Kai SUN ,  Deniz Elizabeth CIVAY ,  David Charles PRITCHARD ,  Andy WEI

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/762 ,  H01L21/3213 ,  H01L21/311 ,  H01L23/522 ,  H01L21/033

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/762 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76841 ,  H01L21/76877 ,  H01L23/5226

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with cross coupled contacts using patterning for cross couple pick-up are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a first lithography to pattern a first shape; performing a second lithography to pattern a second shape overlapping a portion of the first shape; processing the first shape and the second shape to form an isolation region at the overlap; and forming four regions separated by the isolation region. An intermediate semiconductor device is also disclosed.

公开(公告)号：US20180226294A1

公开(公告)日：2018-08-09

申请号：US15425478

申请日：2017-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Eugene STEPHENS ,  David Michael PERMANA ,  Guillaume BOUCHE ,  Andy WEI ,  Mark ZALESKI ,  Anbu Selvam KM MAHALINGAM ,  Craig Michael CHILD, JR. ,  Roderick Alan AUGUR ,  Shyam PAL ,  Linus JANG ,  Xiang HU ,  Akshey SEHGAL

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.

公开(公告)号：US20150261084A1

公开(公告)日：2015-09-17

申请号：US14205569

申请日：2014-03-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Eugene STEPHENS ,  David PRITCHARD

IPC: G03F1/72

CPC classification number: G03F1/72

Abstract: A method is provided, in which a masking reticle including a plurality of pattern blocks is modified, the modifying including: identifying a first pattern block and a second pattern block of the plurality of pattern blocks where at least a first portion of the first pattern block and a second portion of the second pattern block are in parallel relation; and reducing a length of the first portion of the first pattern block when a transverse separation S between corresponding length edges of the first portion of the first pattern block the second portion of the second pattern block falls within a pre-defined forbidden pitch range for the masking reticle. The method may include repeating the identifying and reducing of pairs of pattern blocks on the mask reticle to remove portions of pattern block pairs spaced apart by a transverse separation falling within a forbidden-pitch range.

Abstract translation: 提供了一种方法，其中修改包括多个图案块的掩蔽掩模版，所述修改包括：识别所述多​​个图案块中的第一图案块和第二图案块，其中所述第一图案块的至少第一部分 并且所述第二图案块的第二部分是平行关系的; 以及当第一图案块的第一部分的相应长度边缘之间的横向间隔S与第二图案块的第二部分之间的横向间隔S落入预定义的禁止间距范围内时，减小第一图案块的第一部分的长度， 掩蔽掩模版。 该方法可以包括重复识别和减少掩模掩模版上的图案块对以去除通过落在禁止间距范围内的横向间隔间隔的图案块对的部分。