Invention Application
- Patent Title: ALIGNMENT MARK, METHOD OF MEASURING WAFER ALIGNMENT, AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE METHOD OF MEASURING WAFER ALIGNMENT
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Application No.: US15448325Application Date: 2017-03-02
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Publication No.: US20170261317A1Publication Date: 2017-09-14
- Inventor: Seung Yoon LEE , Chan HWANG , Jeong Jin LEE
- Applicant: Samsung Electronics Co., Ltd.
- Priority: KR10-2016-0030311 20160314
- Main IPC: G01B11/27
- IPC: G01B11/27 ; G01B11/00

Abstract:
A method for measuring wafer alignment is provided. The method includes providing a plurality of first mark patterns extending in a first direction on a wafer, providing at least one second mark pattern on the first mark patterns such that it overlaps and intersects the first mark patterns, irradiating an optical signal onto the first mark patterns and the second mark pattern and obtaining coordinates of the second mark pattern by detecting signals from the second mark pattern.
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