- 专利标题: SEMICONDUCTOR MEMORY DEVICE HAVING LOCAL BIT LINE WITH INSULATION LAYER FORMED THEREIN
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申请号: US15066410申请日: 2016-03-10
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公开(公告)号: US20170263681A1公开(公告)日: 2017-09-14
- 发明人: Shuichi TORIYAMA , Kenichi MUROOKA , Shintaro Nakano , Tatsuya OHGURO
- 申请人: Kabushiki Kaisha Toshiba
- 申请人地址: JP Minato-ku
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JP Minato-ku
- 主分类号: H01L27/24
- IPC分类号: H01L27/24 ; H01L45/00
摘要:
According to one embodiment, a semiconductor memory device includes first conductive layers extending in a first direction and stacked in a second direction intersecting the first direction, a first semiconductor layer extending in the second direction and including a material having one of a first conductivity type and a second conductivity type, a first insulation layer disposed inside the first semiconductor layer, a second conductive layer disposed inside the first insulation layer, and a variable resistance layer disposed between the first conductive layers and the first semiconductor layer.
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