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公开(公告)号：US20160093742A1
公开(公告)日：2016-03-31
申请号：US14663351
申请日：2015-03-19
发明人： Hisayo MOMOSE , Tatsuya OHGURO , Tetsu MOROOKA , Kazuya FUKASE , Shintaro NAKANO , Yuya MAEDA , Shuichi TORIYAMA , Nobuki KANREI
IPC分类号： H01L29/786 , H01L23/00
CPC分类号： H01L29/7869 , H01L29/41733 , H01L29/45 , H01L29/66969 , H01L29/78606
摘要： A semiconductor device according to an embodiment, includes a gate electrode, a first dielectric film, a first oxide semiconductor film, a second dielectric film, a source electrode, a source wire, a drain electrode, and a drain wire. The source wire is arranged on the second dielectric film, and connected to the source electrode. The drain wire is arranged on the second dielectric film, and connected to the drain electrode. At least one of the source wire and the drain wire includes a fringe portion sticking out above a channel region. A barrier film that suppresses intrusion of hydrogen is arranged being in contact with at least one of an upper surface and a lower surface of the fringe portion. A region where the barrier film is not formed is included above the channel region.
摘要翻译： 根据实施例的半导体器件包括栅电极，第一电介质膜，第一氧化物半导体膜，第二电介质膜，源电极，源极线，漏极和漏极线。 源极线布置在第二介电膜上，并连接到源电极。 漏极线布置在第二电介质膜上，并连接到漏电极。 源极线和漏极线中的至少一个包括在沟道区域上方突出的边缘部分。 抑制氢侵入的阻挡膜布置成与边缘部分的上表面和下表面中的至少一个接触。 没有形成阻挡膜的区域包括在沟道区域的上方。
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公开(公告)号：US20170263681A1
公开(公告)日：2017-09-14
申请号：US15066410
申请日：2016-03-10
CPC分类号： H01L27/249 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1253 , H01L45/141 , H01L45/146
摘要： According to one embodiment, a semiconductor memory device includes first conductive layers extending in a first direction and stacked in a second direction intersecting the first direction, a first semiconductor layer extending in the second direction and including a material having one of a first conductivity type and a second conductivity type, a first insulation layer disposed inside the first semiconductor layer, a second conductive layer disposed inside the first insulation layer, and a variable resistance layer disposed between the first conductive layers and the first semiconductor layer.
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公开(公告)号：US20170271405A1
公开(公告)日：2017-09-21
申请号：US15388376
申请日：2016-12-22
IPC分类号： H01L27/24 , H01L45/00 , H01L29/10 , H01L23/528
CPC分类号： H01L27/249 , H01L23/528 , H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L29/1033 , H01L45/04 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146
摘要： A nonvolatile semiconductor memory device according to one embodiment includes: a first wiring extending in a first direction as a longitudinal direction thereof; a second wiring extending in a second direction as a longitudinal direction thereof, the second direction intersecting with the first direction; a memory cell disposed at an intersection portion of the first wiring and the second wiring, the memory cell including a variable resistive element; a select transistor having one end connected to the second wiring; and a third wiring connected to the other end of the select transistor. A semiconductor layer included in the select transistor has a first impurity concentration at the second end. An impurity concentration of the semiconductor layer decrease to a second impurity concentration from the first impurity concentration as approaching to the first end from the second end.
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公开(公告)号：US20150206580A1
公开(公告)日：2015-07-23
申请号：US14491086
申请日：2014-09-19
发明人： Shuichi TORIYAMA
IPC分类号： G11C13/00
CPC分类号： G11C13/0007 , G11C13/0028 , G11C13/0069 , G11C2013/008 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/78
摘要： A semiconductor memory device according to an embodiment comprises: a plurality of first lines extending in a first direction perpendicular to a substrate surface and arranged with a certain pitch in a second direction parallel to the substrate surface; a plurality of second lines extending in the second direction and arranged with a certain pitch in the first direction; a memory cell provided at an intersection of the first line and the second line and including a variable resistance element; a third line provided extending in the second direction between the plurality of second lines; and a control circuit capable of executing a first operation that changes a resistance value of the variable resistance element by applying a voltage to the memory cell via the first line and the second line, and a second operation that supplies heat to the memory cell using the third line.
摘要翻译： 根据实施例的半导体存储器件包括：沿垂直于衬底表面的第一方向延伸的多个第一线，并且在平行于衬底表面的第二方向上以一定间距布置; 多个第二线，沿第二方向延伸，并以第一方向以一定间距布置; 存储单元，设置在所述第一线路和所述第二线路的交点处，并且包括可变电阻元件; 设置在所述多个第二线之间沿所述第二方向延伸的第三线; 以及控制电路，其能够执行通过经由第一线路和第二线路向存储器单元施加电压来改变可变电阻元件的电阻值的第一操作，以及第二操作，其使用 第三行。
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公开(公告)号：US20160163981A1
公开(公告)日：2016-06-09
申请号：US14941946
申请日：2015-11-16
发明人： Shuichi TORIYAMA , Reika ICHIHARA
CPC分类号： H01L45/145 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C2213/15 , G11C2213/71 , H01L27/2454 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/146 , H01L45/147
摘要： According to one embodiment, a semiconductor memory device includes a plurality of first wirings, a plurality of second wirings, a variable resistance layer, a first barrier insulating layer, and a second barrier insulating layer. The first wirings are disposed at predetermined pitches in a first direction intersecting with a substrate. The second wirings are disposed at predetermined pitches in a second direction intersecting with the first direction. The second wirings are formed to extend in the first direction. The variable resistance layer is disposed between the first wiring and the second wiring. The variable resistance layer is disposed at a position where the first wiring intersects with the second wiring. The first barrier insulating layer is disposed between the first wiring and the variable resistance layer. The second barrier insulating layer is disposed between the second wiring and the variable resistance layer.
摘要翻译： 根据一个实施例，半导体存储器件包括多个第一布线，多个第二布线，可变电阻层，第一阻挡绝缘层和第二阻挡绝缘层。 第一布线以与基板相交的第一方向以预定间距布置。 第二布线以与第一方向相交的第二方向以预定间距布置。 第二配线形成为沿第一方向延伸。 可变电阻层设置在第一布线和第二布线之间。 可变电阻层设置在第一布线与第二布线相交的位置。 第一阻挡绝缘层设置在第一布线和可变电阻层之间。 第二阻挡绝缘层设置在第二布线和可变电阻层之间。
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公开(公告)号：US20150255122A1
公开(公告)日：2015-09-10
申请号：US14491058
申请日：2014-09-19
发明人： Shuichi TORIYAMA
CPC分类号： G11C5/06 , G11C13/0002 , G11C13/0007 , G11C13/0011 , G11C13/0069 , G11C2013/0073 , G11C2213/18 , G11C2213/71 , H01L27/249 , H01L45/08
摘要： A non-volatile semiconductor storage device according to each of the embodiments includes a cell array that includes a plurality of first wires extending in a first direction, a plurality of second wires extending in a second direction crossing the first direction, and a plurality of memory cells each provided at an intersection between each of the first wires and each of the second wires. Each memory cell includes a variable resistance film of which resistance varies depending on a state of a filament in a medium. Each cell array has a first portion at which a distance between the first wire and the second wire is minimized and a second portion at which a distance between the first wire and the second wire is larger than the first portion at the intersection between each of the first wires and each of the second wires.
摘要翻译： 根据实施例中的每一个的非易失性半导体存储装置包括：单元阵列，其包括沿第一方向延伸的多个第一布线，沿与第一方向交叉的第二方向延伸的多个第二布线;多个存储器 每个单元设置在每个第一布线和每条第二布线之间的交点处。 每个存储单元包括其电阻根据介质中的细丝的状态而变化的可变电阻膜。 每个单元阵列具有第一部分，第一线和第二线之间的距离最小化;第二部分，第一线和第二线之间的距离大于第一线和第二线之间的交点处的第一部分 第一线和每条第二条线。
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公开(公告)号：US20130223173A1
公开(公告)日：2013-08-29
申请号：US13773954
申请日：2013-02-22
发明人： Yusuke HIGASHI , Haruki TODA , Kenichi MUROOKA , Satoru TAKASE , Yuichiro MITANI , Shuichi TORIYAMA
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C7/04 , G11C11/1695 , G11C13/0002 , G11C13/0023 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C16/22 , G11C2213/71 , G11C2213/72
摘要： According to one embodiment, a semiconductor memory device includes a memory cell array including blocks, each block being capable of executing a write, read, or erase operation independently of other blocks. A control portion is configured to execute the operation of a first block among the blocks in a first cycle, set a selection inhibited region within a range of a predetermined distance from the first block, until a temperature relaxation time for relaxing a temperature of the first block has elapsed, set a region except the selection inhibited region among the blocks as a second block, and execute the operation of the second block in a second cycle.
摘要翻译： 根据一个实施例，半导体存储器件包括包括块的存储单元阵列，每个块能够独立于其它块执行写入，读取或擦除操作。 控制部分被配置为在第一周期中执行块中的第一块的操作，将选择禁止区域设置在距离第一块的预定距离的范围内，直到用于放宽第一块的温度的温度弛豫时间 块已经过去，将除块中的选择禁止区域之外的区域设置为第二块，并且在第二周期中执行第二块的操作。
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