Invention Application
- Patent Title: Multi-chip package and manufacturing method
-
Application No.: US15611812Application Date: 2017-06-02
-
Publication No.: US20170271288A1Publication Date: 2017-09-21
- Inventor: Antti Iihola , Risto Tuominen
- Applicant: GE Embedded Electronics Oy
- Priority: FI20085739 20080722
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/538 ; H01L25/00 ; H01L25/065 ; H05K1/18 ; H05K3/30

Abstract:
Manufacturing method and a multi-chip package, which comprises a conductor pattern and insulation, and, inside the insulation, a first component, the contact terminals of which face towards the conductor pattern and are conductively connected to the conductor pattern. The multi-chip package also comprises inside the insulation a second semiconductor chip, the contact terminals of which face towards the same conductor pattern and are conductively connected through contact elements to this conductor pattern. The semiconductor chips are located in such a way that the first semiconductor chip is located between the second semiconductor chip and the conductor pattern.
Information query
IPC分类: