Invention Application
- Patent Title: PADS AND PIN-OUTS IN THREE DIMENSIONAL INTEGRATED CIRCUITS
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Application No.: US15620142Application Date: 2017-06-12
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Publication No.: US20170278850A1Publication Date: 2017-09-28
- Inventor: Raminda Udaya Madurawe
- Applicant: CALLAHAN CELLULAR L.L.C.
- Main IPC: H01L27/118
- IPC: H01L27/118 ; G11C11/413 ; G11C5/06 ; H01L21/28 ; H01L23/36 ; H01L23/48
Abstract:
A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a circuit; and a memory array positioned above or below the substrate and coupled to a circuit to program the memory array.
Public/Granted literature
- US09978773B2 Pads and pin-outs in three dimensional integrated circuits Public/Granted day:2018-05-22
Information query
IPC分类:
