Invention Application
- Patent Title: TECHNIQUES FOR ENFORCING CONTROL FLOW INTEGRITY USING BINARY TRANSLATION
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Application No.: US15430652Application Date: 2017-02-13
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Publication No.: US20170316201A1Publication Date: 2017-11-02
- Inventor: KOICHI YAMADA , PALANIVELRAJAN SHANMUGAVELAYUTHAM , SRAVANI KONDA
- Applicant: INTEL CORPORATION
- Applicant Address: US CA SANTA CLARA
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA SANTA CLARA
- Main IPC: G06F21/54
- IPC: G06F21/54 ; G06F9/44 ; G06F9/45 ; G06F9/455

Abstract:
Various embodiments are generally directed to an apparatus, method and other techniques to determine a valid target address for a branch instruction from information stored in a relocation table, a linkage table, or both, the relocation table and the linkage table associated with a binary file and store the valid target address in a table in memory, the valid target address to validate a target address for a translated portion of a routine of the binary file.
Public/Granted literature
- US10268819B2 Techniques for enforcing control flow integrity using binary translation Public/Granted day:2019-04-23
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