- 专利标题: SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
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申请号: US15609535申请日: 2017-05-31
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公开(公告)号: US20170366004A1公开(公告)日: 2017-12-21
- 发明人: Mutsuo NISHIKAWA , Kazuhiro MATSUNAMI , Katsuhiro SHIMAZU
- 申请人: FUJI ELECTRIC CO., LTD.
- 申请人地址: JP Kawasaki-shi
- 专利权人: FUJI ELECTRIC CO., LTD.
- 当前专利权人: FUJI ELECTRIC CO., LTD.
- 当前专利权人地址: JP Kawasaki-shi
- 优先权: JP2016-120281 20160616
- 主分类号: H02H9/04
- IPC分类号: H02H9/04 ; H01L23/528 ; H01L27/02 ; H01L27/06 ; H01L27/088 ; H03K3/356
摘要:
A protection circuit includes a first PMOS and a first PDMOS receiving input of voltage of a voltage dividing point of voltage input from an external power supply terminal, and a second PMOS and a second PDMOS receiving input of drain output voltage of the first PDMOS. The first PMOS is connected on the external power supply terminal side of the first PDMOS, and the second PMOS is connected on the external power supply terminal side of the second PDMOS. During overvoltage application, the voltage of the voltage dividing point is clamped to the breakdown voltage of a Zener diode, the second PDMOS turns OFF, and supply to an integrated circuit protected from overvoltage is cut off. When the voltage source is connected in reverse, parasitic diodes of the first and second PMOSs are reverse-biased and the flow of current in a path through the parasitic diodes is inhibited.
公开/授权文献
- US10381827B2 Semiconductor integrated circuit device 公开/授权日:2019-08-13
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