Invention Application
- Patent Title: ANALOG FRACTIONAL-N PHASE-LOCKED LOOP
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Application No.: US15629509Application Date: 2017-06-21
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Publication No.: US20170366376A1Publication Date: 2017-12-21
- Inventor: Haisong Wang , Xiang Gao , Olivier Burg , Cao-Thong Tu
- Applicant: Marvell World Trade Ltd.
- Main IPC: H04L27/20
- IPC: H04L27/20 ; H03L7/197 ; H03L7/087 ; H04L25/03 ; H03L7/081

Abstract:
An analog fractional-N phase-locked loop includes an oscillator loop having a reference input, a feedback input, and a loop output, and a fractional feedback divider configured to divide signals on the loop output by a divisor. Output of the fractional feedback divider is fed back to the feedback input. A compensation circuit is coupled to, and configured to apply a time delay to, the reference input or the feedback input, to compensate for delay introduced by the fractional feedback divider. The compensation circuit may be a digital-to-time converter configured to convert a digital delay signal into the time delay. The digital-to-time converter may be coupled to the reference input to delay signals to match feedback delay introduced by the fractional feedback divider, or to the feedback input to subtract the time delay to cancel feedback delay introduced by the fractional feedback divider.
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