Invention Application
- Patent Title: IP Route Caching with Two Search Stages on Prefix Length
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Application No.: US15186477Application Date: 2016-06-19
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Publication No.: US20170366502A1Publication Date: 2017-12-21
- Inventor: Fima Kravchik , Pedro Reviriego , Salvatore Pontarelli , Aviv Kfir , Amir Roitshtein , Gil Levy
- Applicant: Mellanox Technologies TLV Ltd.
- Main IPC: H04L29/12
- IPC: H04L29/12 ; H04L29/08 ; H04L12/741

Abstract:
A data packet is received in a network element. The network element has a cache memory in which cache entries represent a portion of addresses stored in a main memory, The destination address and the cache entries each comprise a binary number. A first determination is made that a number M of the most significant bits of a cache entry and the destination address are identical. A second determination is made that an additional number M+L of the most significant bits of a cache entry and the destination address are identical. Routing information is then retrieved the cache memory, and the packet processed according to the routing information.
Public/Granted literature
- US10171419B2 IP route caching with two search stages on prefix length Public/Granted day:2019-01-01
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