公开(公告)号：US11516135B2

公开(公告)日：2022-11-29

申请号：US16746879

申请日：2020-01-19

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Niv Aibester ,  Aviv Kfir ,  Gil Levy ,  Liron Mula

IPC: H04L41/16 ,  H04L47/20 ,  H04L47/32 ,  H04L47/783 ,  H04L47/2441

Abstract: Apparatus for global policing of a bandwidth of a flow, the apparatus including a network device including a local policer configured to perform bandwidth policing on the flow within the network device, and a communications module configured to: send local policer state information from the local policer to a remote global policer, and receive policer state information from the remote global policer and update the local policer state information based on the remote global policer state information, Related apparatus and methods are also provided.

公开(公告)号：US20210359943A1

公开(公告)日：2021-11-18

申请号：US17224208

申请日：2021-04-07

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Gil Levy ,  Aviv Kfir ,  Matty Kadosh ,  Salvatore Pontarelli ,  Pedro Reviriego

IPC: H04L12/745 ,  H04L12/743 ,  H04L12/751 ,  H04L12/721 ,  H04L12/717

Abstract: In one embodiment, a packet processing apparatus includes interfaces, a memory to store a representation of a routing table as a binary search tree of address prefixes, and store a marker with an embedded prefix including k marker bits providing a marker for an address prefix of a node corresponding to a prefix length greater than k, and n additional bits, such that the k marker bits concatenated with the n additional bits provide another address prefix, packet processing circuitry configured upon receiving a data packet having a destination address, to traverse the binary search tree to find a longest prefix match, compare a key with the k marker bits, extract an additional n bits from the destination address, and compare the extracted n bits with the n additional bits, and process the data packet in accordance with a forwarding action indicated by the longest prefix match.

公开(公告)号：US11005770B2

公开(公告)日：2021-05-11

申请号：US16442508

申请日：2019-06-16

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Barak Gafni ,  Eitan Zahavi ,  Gil Levy ,  Aviv Kfir ,  Liron Mula

IPC: H04W72/04 ,  H04L12/835 ,  H04L12/825 ,  H04L12/801

Abstract: Network communication is carried out by sending packets from a source network interface toward a destination network interface, receiving one of the packets in an intermediate switch of the network, determining that the intermediate switch is experiencing network congestion, generating in the intermediate switch a congestion notification packet for the received packet, and transmitting the congestion notification packet from the intermediate switch to the source network interface via the network. The received packet is forwarded from the intermediate switch toward the destination network interface. The source network interface may modify a rate of packet transmission responsively to the congestion notification packet.

公开(公告)号：US20210067448A1

公开(公告)日：2021-03-04

申请号：US16559658

申请日：2019-09-04

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Tom Remen ,  Nir Monovich ,  Gil Levy ,  Aviv Kfir ,  Linor Nehab

IPC: H04L12/743 ,  H04L12/741 ,  H04L29/06

Abstract: A network element includes ports, a hardware fabric, a packet classifier and control logic. The ports are configured to transmit and receive packets over a network. The fabric is configured to forward the packets between the ports. The packet classifier is configured to receive at least some of the packets and to specify an action to be applied to a packet in accordance with a set of rules. The classifier includes (i) multiple Ternary Content Addressable Memories (TCAMs), each TCAM configured to match the packet to a respective subset of the set of rules and to output a match result, and (ii) circuitry configured to specify the action to be applied to the packet based on match results produced for the packet by the multiple TCAMs, and based on a priority defined among the multiple TCAMs. The control logic is configured to apply the specified action to the packet.

公开(公告)号：US10684960B2

公开(公告)日：2020-06-16

申请号：US15830021

申请日：2017-12-04

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Gil Levy ,  Fima Kravchik

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/126 ,  G06F16/2455

Abstract: A network element includes a data structure, a cache memory and circuitry. The data structure is configured to store multiple rules specifying processing of packets received from a communication network. The cache memory is configured to cache multiple rules including a subset of the rules stored in the data structure. Each rule that is cached in the cache memory has a respective cost value corresponding to a cost of retrieving the rule from the data structure. The circuitry is configured to receive one or more packets from the communication network, to process the received packets in accordance with one or more of the rules, by retrieving the rules from the cache memory when available, or from the data structure otherwise, to select a rule to be evicted from the cache memory, based on one or more respective cost values of the rules currently cached, and to evict the selected rule.

公开(公告)号：US20200145315A1

公开(公告)日：2020-05-07

申请号：US16181395

申请日：2018-11-06

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Gil Levy ,  Liron Mula ,  Aviv Kfir

IPC: H04L12/26 ,  H04L29/08 ,  H04L12/707

Abstract: A network switch includes multiple ports that serve as ingress ports and egress ports for connecting to a communication network, and processing circuitry. The processing circuitry is configured to receive packets via the ingress ports, select one or more of the packets for mirroring, create mirror copies of the selected packets and output the mirror copies for analysis, mark the packets for which mirror copies have been created with mirror-duplicate indications, and forward the packets to the egress ports, including the packets that are marked with the mirror-duplicate indications.

公开(公告)号：US10237156B2

公开(公告)日：2019-03-19

申请号：US15361528

申请日：2016-11-28

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Oded Belfer ,  George Elias ,  Gil Levy

IPC: H04L12/26

Abstract: A network element includes multiple interfaces and circuitry. The interfaces are configured to connect to a communication system. The circuitry is configured to receive via an ingress interface a packet that includes an Error Detection Code (EDC) field including an input EDC value, to determine an input timestamp indicative of a time-of-arrival of the received packet at the network element, and overwrite at least part of the input EDC value in the EDC field of the packet with the input timestamp, to estimate for the packet a traversal latency between reception at the ingress interface and transmission via a selected egress interface, based at least on the input timestamp, and to produce a deliverable version of the packet by writing an output EDC value to the EDC field, and send the deliverable version of the packet via the selected egress interface.

公开(公告)号：US20190036821A1

公开(公告)日：2019-01-31

申请号：US15663758

申请日：2017-07-30

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Gil Levy ,  Pedro Reviriego ,  Aviv Kfir ,  Salvatore Pontarelli

IPC: H04L12/747 ,  G06F12/0868 ,  H04L12/743

Abstract: Communication apparatus includes a TCAM, which stores a corpus of rules, including respective sets of unmasked and masked bits. The rules conform to respective rule patterns, each defining a different, respective sequence of masked and unmasked bits to which one or more of the rules conform. A RAM caches rule entries corresponding to rules belonging to one or more of the rule patterns that have been selected for caching. Decision logic extracts respective classification keys from data packets, each key including a string of bits extracted from selected fields in a given data packet, and classifies the data packets by first matching the respective classification keys to the cached rule entries in the RAM and, when no match is found in the RAM, by matching the respective classification keys to the rules in the TCAM.

公开(公告)号：US10148571B2

公开(公告)日：2018-12-04

申请号：US15186562

申请日：2016-06-20

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Aviv Kfir ,  Pedro Reviriego ,  Salvatore Pontarelli ,  Gil Levy

IPC: H04L12/745 ,  H04L12/753

Abstract: A routing table is represented as a binary search tree ordered by prefix lengths. Markers are placed to guide accessing nodes in designated subtrees to search for a longest prefix match with destination addresses of data packet. Destination descendant nodes in remote hierarchical levels of the tree are associated with the markers. The traversal of the binary search tree is conducted by accessing the respective destination descendant nodes while avoiding accessing nodes in intermediate hierarchical levels. The packet is processed using the longest prefix match.

公开(公告)号：US20180343613A1

公开(公告)日：2018-11-29

申请号：US15607494

申请日：2017-05-28

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Gil Levy ,  Liron Mula ,  Aviv Kfir ,  Lavi Koch

IPC: H04W52/02 ,  G06F1/32

CPC classification number: H04W52/0222 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3278 ,  H04W52/0206

Abstract: A network element includes circuitry and multiple ports. The ports are configured to transmit packets to a common destination via multiple paths of a communication network. Each port includes multiple serializers that serially transmit the packets over respective physical lanes. The power consumed by each port is a nonlinear function of the number of serializers activated in the port. The circuitry is configured to select one or more serializers among the ports to (i) meet a throughput demand via the ports and (ii) minimize an overall power consumed by the ports under a constraint of the nonlinear function, and to activate only the selected serializers. The circuitry is configured to choose for a packet received in the network element and destined to the common destination a port in which at least one of the serializers is activated, and to transmit the packet to the common destination via the chosen port.