公开(公告)号：US10015112B2

公开(公告)日：2018-07-03

申请号：US14961923

申请日：2015-12-08

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Amir Roitshtein ,  Niv Aibester ,  Barak Gafni ,  George Elias

IPC: H04L12/931 ,  H04L12/861 ,  H04L12/741

CPC classification number: H04L49/201 ,  H04L45/745 ,  H04L49/205 ,  H04L49/9005

Abstract: Communication apparatus includes multiple interfaces connected to a packet data network. A memory is coupled to the interfaces and configured as a buffer to contain packets received through ingress interfaces while awaiting transmission to the network via respective egress interfaces. Packet processing logic is configured, upon receipt of a multicast packet through an ingress interface, to identify a number of the egress interfaces through which respective copies of the multicast packet are to be transmitted, to allocate a space in the buffer for storage of a single copy of the multicast packet, to replicate and transmit multiple copies of the stored copy of the multicast packet through the egress interfaces, to maintain a count of the replicated copies that have been transmitted, and when the count reaches the identified number, to release the allocated space in the buffer.

公开(公告)号：US20170366502A1

公开(公告)日：2017-12-21

申请号：US15186477

申请日：2016-06-19

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Fima Kravchik ,  Pedro Reviriego ,  Salvatore Pontarelli ,  Aviv Kfir ,  Amir Roitshtein ,  Gil Levy

IPC: H04L29/12 ,  H04L29/08 ,  H04L12/741

CPC classification number: H04L61/6009 ,  H04L45/54 ,  H04L45/74 ,  H04L45/7453 ,  H04L67/2842

Abstract: A data packet is received in a network element. The network element has a cache memory in which cache entries represent a portion of addresses stored in a main memory, The destination address and the cache entries each comprise a binary number. A first determination is made that a number M of the most significant bits of a cache entry and the destination address are identical. A second determination is made that an additional number M+L of the most significant bits of a cache entry and the destination address are identical. Routing information is then retrieved the cache memory, and the packet processed according to the routing information.

公开(公告)号：US10250530B2

公开(公告)日：2019-04-02

申请号：US15063527

申请日：2016-03-08

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Niv Aibester ,  Amir Roitshtein ,  Barak Gafni ,  George Elias ,  Itamar Rabenstein

IPC: H04L12/861

Abstract: Communication apparatus includes multiple interfaces configured to be connected to a packet data network for receiving and forwarding of data packets of multiple types. A memory is coupled to the interfaces and configured as a buffer to contain packets received through the ingress interfaces while awaiting transmission to the network via the egress interfaces. Packet processing logic is configured to maintain multiple transmit queues, which are associated with respective ones of the egress interfaces, and to place both first and second queue entries, corresponding to first and second data packets of the first and second types, respectively, in a common transmit queue for transmission through a given egress interface, while allocating respective spaces in the buffer to store the first and second data packets against separate, first and second buffer allocations, which are respectively assigned to the first and second types of the data packets.

公开(公告)号：US20170264571A1

公开(公告)日：2017-09-14

申请号：US15063527

申请日：2016-03-08

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Niv Aibester ,  Amir Roitshtein ,  Barak Gafni ,  George Elias ,  Itamar Rabenstein

IPC: H04L12/861

CPC classification number: H04L49/9005

Abstract: Communication apparatus includes multiple interfaces configured to be connected to a packet data network for receiving and forwarding of data packets of multiple types. A memory is coupled to the interfaces and configured as a buffer to contain packets received through the ingress interfaces while awaiting transmission to the network via the egress interfaces. Packet processing logic is configured to maintain multiple transmit queues, which are associated with respective ones of the egress interfaces, and to place both first and second queue entries, corresponding to first and second data packets of the first and second types, respectively, in a common transmit queue for transmission through a given egress interface, while allocating respective spaces in the buffer to store the first and second data packets against separate, first and second buffer allocations, which are respectively assigned to the first and second types of the data packets.

公开(公告)号：US10171419B2

公开(公告)日：2019-01-01

申请号：US15186477

申请日：2016-06-19

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Fima Kravchik ,  Pedro Reviriego ,  Salvatore Pontarelli ,  Aviv Kfir ,  Amir Roitshtein ,  Gil Levy

IPC: H04L12/56 ,  H04L29/12 ,  H04L12/741 ,  H04L29/08 ,  H04L12/743

Abstract: A data packet is received in a network element. The network element has a cache memory in which cache entries represent a portion of addresses stored in a main memory, The destination address and the cache entries each comprise a binary number. A first determination is made that a number M of the most significant bits of a cache entry and the destination address are identical. A second determination is made that an additional number M+L of the most significant bits of a cache entry and the destination address are identical. Routing information is then retrieved the cache memory, and the packet processed according to the routing information.

公开(公告)号：US20170163567A1

公开(公告)日：2017-06-08

申请号：US14961923

申请日：2015-12-08

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Amir Roitshtein ,  Niv Aibester ,  Barak Gafni ,  George Elias

IPC: H04L12/931 ,  H04L12/861

CPC classification number: H04L49/201 ,  H04L45/745 ,  H04L49/205 ,  H04L49/9005

Abstract: Communication apparatus includes multiple interfaces connected to a packet data network. A memory is coupled to the interfaces and configured as a buffer to contain packets received through ingress interfaces while awaiting transmission to the network via respective egress interfaces. Packet processing logic is configured, upon receipt of a multicast packet through an ingress interface, to identify a number of the egress interfaces through which respective copies of the multicast packet are to be transmitted, to allocate a space in the buffer for storage of a single copy of the multicast packet, to replicate and transmit multiple copies of the stored copy of the multicast packet through the egress interfaces, to maintain a count of the replicated copies that have been transmitted, and when the count reaches the identified number, to release the allocated space in the buffer.