Invention Application
- Patent Title: SURFACE FINISHES FOR INTERCONNECTION PADS IN MICROELECTRONIC STRUCTURES
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Application No.: US15545670Application Date: 2015-02-25
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Publication No.: US20180019219A1Publication Date: 2018-01-18
- Inventor: Srinivas V. Pietambaram , Kyu Oh Lee
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- International Application: PCT/US2015/017435 WO 20150225
- Main IPC: H01L23/00
- IPC: H01L23/00 ; B23K35/26 ; H01L23/498 ; C22C13/00 ; C22C19/03

Abstract:
A surface finish may be formed in a microelectronic structure, wherein the surface finish may include a multilayer interlayer structure. Thus, needed characteristics, such as compliance and electro-migration resistance, of the interlayer structure may be satisfied by different material layers, rather attempting to achieve these characteristics with a single layer. In one embodiment, the multilayer interlayer structure may comprises a two-layer structure, wherein a first layer is formed proximate a solder interconnect and comprises a material which forms a ductile joint with the solder interconnect, and a second layer comprising a material having strong electro-migration resistance formed between the first layer and an interconnection pad. In a further embodiment, third layer may be formed adjacent the interconnection pad comprising a material which forms a ductile joint with the interconnection pad.
Public/Granted literature
- US10121752B2 Surface finishes for interconnection pads in microelectronic structures Public/Granted day:2018-11-06
Information query
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