公开(公告)号：US12218071B2

公开(公告)日：2025-02-04

申请号：US18208785

申请日：2023-06-12

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Sri Ranga Sai Boyapati ,  Robert A. May ,  Kristof Darmawikarta ,  Javier Soto Gonzalez ,  Kwangmo Lim

IPC: H01L23/538 ,  H01L23/00

Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.

公开(公告)号：US20240186228A1

公开(公告)日：2024-06-06

申请号：US18061237

申请日：2022-12-02

Applicant: Intel Corporation

Inventor： Haobo Chen ,  Bohan Shan ,  Kyle J. Arrington ,  Yiqun Bai ,  Kristof Darmawikarta ,  Gang Duan ,  Jeremy D. Ecton ,  Hongxia Feng ,  Xiaoying Guo ,  Ziyin Lin ,  Brandon Christian Marin ,  Bai Nie ,  Srinivas V. Pietambaram ,  Dingying Xu

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L21/486 ,  H01L23/49827

Abstract: In one embodiment, an integrated circuit package substrate includes a core layer comprising a dielectric material and a plurality of metal vias within the core layer. The dielectric material includes Silicon, Oxygen, and at least one of Boron or Phosphorus. The metal vias electrically couple a first side of the core layer and a second side of the core layer opposite the first side. The package substrate further includes a plurality of build-up layers on the core layer, the build-up layers comprising metal vias electrically connected to the metal vias of the core layer.

公开(公告)号：US20240178146A1

公开(公告)日：2024-05-30

申请号：US18060080

申请日：2022-11-30

Applicant: Intel Corporation

Inventor： Benjamin T. Duong ,  Whitney Bryks ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Gang Duan ,  Ravindranath Vithal Mahajan

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/15 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5384 ,  H01L23/15 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/13023 ,  H01L2924/15165 ,  H01L2924/15311

Abstract: Disclosed herein are microelectronic assemblies including strengthened glass cores, as well as related devices and methods. In some embodiments, a microelectronic assembly may include a glass core having a surface, a first region having a first concentration of ions extending from the surface of the core to a first depth; a second region having a second concentration of ions greater than the first concentration of ions, the second region between the first region and the surface of the core; a dielectric with a conductive pathway at the surface of the glass core; and a die electrically coupled to the conductive pathway in the dielectric at the surface of the core by an interconnect.

公开(公告)号：US20240128247A1

公开(公告)日：2024-04-18

申请号：US18046635

申请日：2022-10-14

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Gang Duan ,  Jeremy Ecton ,  Suddhasattwa Nad ,  Hiroki Tanaka

IPC: H01L25/16 ,  H01F27/02 ,  H01F27/28 ,  H01F27/29 ,  H01F41/00 ,  H01F41/04 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L25/16 ,  H01F27/022 ,  H01F27/2804 ,  H01F27/292 ,  H01F41/005 ,  H01F41/041 ,  H01L21/486 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L21/4853 ,  H01L2224/16235 ,  H01L2224/16267 ,  H01L2924/19042 ,  H01L2924/19103

Abstract: Embodiments described herein enable a microelectronic assembly that includes: a first substrate comprising glass and at least one inductor, the first substrate having a first side and an opposing second side; a second substrate coupled to the first side of the first substrate; and a plurality of integrated circuit (IC) dies. A first subset of the plurality of IC dies is directly coupled to the second side of the first substrate, a second subset of the plurality of IC dies is directly coupled to the second substrate adjacent to the first substrate, and a third subset of the plurality of IC dies is embedded in the second substrate between the first substrate and the second subset of the plurality of IC dies.

公开(公告)号：US20240120305A1

公开(公告)日：2024-04-11

申请号：US17938784

申请日：2022-10-07

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Suddhasattwa Nad ,  Srinivas V. Pietambaram ,  Mohammad Mamunur Rahman

IPC: H01L23/00 ,  H01L23/538

CPC classification number: H01L24/16 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/14 ,  H01L24/32 ,  H01L24/73 ,  H01L24/13 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/13686 ,  H01L2224/1403 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Embodiments of a microelectronic assembly includes: a package substrate and an integrated circuit (IC) die coupled to a surface of the package substrate by first interconnects and second interconnects, the first interconnects and the second interconnects comprising solder. The first interconnects are larger than the second interconnects, the first interconnects and the second interconnects further comprise bumps on the IC die and bond-pads on the surface of the package substrate, with the solder coupled to the bumps and the bond-pads, lateral sides of the bumps have a coating of a material that prevents solder wicking, and the surface of the package substrate includes insulative baffles between the bond-pads.

公开(公告)号：US20230317619A1

公开(公告)日：2023-10-05

申请号：US17711978

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Ravindranath V. Mahajan ,  Srikant Nekkanty ,  Srinivas V. Pietambaram ,  Veronica Strong ,  Xiao Lu ,  Tarek A. Ibrahim ,  Karumbu Nathan Meyyappan ,  Dingying Xu ,  Kristof Darmawikarta

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L23/5384

Abstract: A microelectronic structure, a semiconductor package including the same, and a method of forming same. The microelectronic structures includes: a substrate defining a cavity therein; a bridge die within the cavity, the bridge die to electrically couple a pair of dies to be provided on a surface of the substrate; an electrical coupling layer between a top surface of the cavity and a bottom surface of the bridge die. The electrical coupling layer includes: a non-conductive component including a die bonding film and defining holes therein; and electrically conductive structures in the holes, the electrically conductive structures electrically coupling the substrate with the bridge die.

公开(公告)号：US20230095846A1

公开(公告)日：2023-03-30

申请号：US17485039

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Benjamin T. Duong ,  Srinivas V. Pietambaram ,  Aleksandar Aleksov ,  Helme Castro De La Torre ,  Kristof Darmawikarta ,  Darko Grujicic ,  Sashi S. Kandanur ,  Suddhasattwa Nad ,  Rengarajan Shanmugam ,  Thomas I. Sounart ,  Marcel A. Wall

IPC: H01L23/498 ,  H01G4/33 ,  H01L21/48

Abstract: Glass substrates having transverse capacitors for use with semiconductor packages and related methods are disclosed. An example semiconductor package includes a glass substrate having a through glass via between a first surface and a second surface opposite the first surface. A transverse capacitor is located in the through glass via. The transverse capacitor includes a dielectric material positioned in a first portion of the through glass via, a first barrier/seed layer positioned in a second portion of the through glass via, and a first conductive material positioned in a third portion of the through glass via.

公开(公告)号：US20230094686A1

公开(公告)日：2023-03-30

申请号：US17485034

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Srinivas V. Pietambaram ,  Aleksandar Aleksov

IPC: H01L23/522 ,  H01L23/15 ,  H01L23/528 ,  H01L23/50 ,  H01L21/768

Abstract: Glass layers having partially embedded conductive layers for power delivery in semiconductor packages and related methods are disclosed. An example semiconductor package includes a core layer having a thickness between a first surface opposite a second surface. The core layer includes a trench provided in the first surface. The trench partially extending between the first surface and the second surface. An electrically conductive material is positioned in the trench. A trace is provided on the conductive material. The trace is offset in a direction away from the first surface and away from the second surface of the core layer.

公开(公告)号：US20220375865A1

公开(公告)日：2022-11-24

申请号：US17323253

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Krishna Bharath ,  Sai Vadlamani ,  Pooya Tadayon ,  Tarek A. Ibrahim

IPC: H01L23/538 ,  H01L49/02 ,  H01L23/64 ,  H01L25/065

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a glass substrate having a plurality of conductive through-glass vias (TGV); a magnetic core inductor including: a first conductive TGV at least partially surrounded by a magnetic material; and a second conductive TGV electrically coupled to the first TGV; a first die in a first dielectric layer, wherein the first dielectric layer is on the glass substrate; and a second die in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the second die is electrically coupled to the magnetic core inductor.

公开(公告)号：US11309192B2

公开(公告)日：2022-04-19

申请号：US16000205

申请日：2018-06-05

Applicant: Intel Corporation

Inventor： Kristof Kuwawi Darmawikarta ,  Robert May ,  Sri Ranga Sai Boyapati ,  Srinivas V. Pietambaram ,  Chung Kwang Christopher Tan ,  Aleksandar Aleksov

IPC: H01L21/48 ,  H01L23/498

Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.