Invention Application
- Patent Title: METHOD AND APPARATUS FOR REDUCING MEMORY ACCESS LATENCY
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Application No.: US15272894Application Date: 2016-09-22
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Publication No.: US20180081563A1Publication Date: 2018-03-22
- Inventor: David A. Roberts
- Applicant: Advanced Micro Devices, Inc.
- Main IPC: G06F3/06
- IPC: G06F3/06

Abstract:
Logic such as a memory controller writes primary data from an incoming write request as well as corresponding replicated primary data (which is a copy of the primary data) to one or more different memory banks of random access memory in response to determining a memory access contention condition for the address (including a range of addresses) corresponding to the incoming write request. When the memory bank containing the primary data is busy servicing a write request, such as to another row of memory in the bank, a read request for the primary data is serviced by reading the replicated primary data from the different memory bank of the random access memory to service the incoming read request.
Public/Granted literature
- US10515671B2 Method and apparatus for reducing memory access latency Public/Granted day:2019-12-24
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