Invention Application
- Patent Title: HIGH RELIABILITY WAFER LEVEL SEMICONDUCTOR PACKAGING
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Application No.: US15823744Application Date: 2017-11-28
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Publication No.: US20180082913A1Publication Date: 2018-03-22
- Inventor: Yu-Te HSIEH
- Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Applicant Address: US AZ Phoenix
- Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee Address: US AZ Phoenix
- Main IPC: H01L23/10
- IPC: H01L23/10 ; H01L23/00 ; H01L21/302 ; H01L23/31 ; H01L23/498 ; H01L23/48

Abstract:
Implementations of semiconductor packages may include: a semiconductor wafer, a glass lid fixedly coupled to a first side of the semiconductor die by an adhesive, a redistribution layer coupled to a second side of the semiconductor die, and a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer coupled to the semiconductor die. The adhesive may be located in a trench around a perimeter of the semiconductor die and located in a corresponding trench around a perimeter of the glass lid.
Public/Granted literature
- US10290556B2 High reliability wafer level semiconductor packaging Public/Granted day:2019-05-14
Information query
IPC分类: