METHOD FOR DEFINING A GAP HEIGHT WITHIN AN IMAGE SENSOR PACKAGE

    公开(公告)号:US20250022898A1

    公开(公告)日:2025-01-16

    申请号:US18902029

    申请日:2024-09-30

    Inventor: Yu-Te HSIEH

    Abstract: According to an aspect, an image sensor package includes a substrate, an image sensor die coupled to the substrate, a light transmitting member, and a plurality of pillar members disposed between and contacting the image sensor die and the light transmitting member. A height of the plurality of pillar members defines a gap height between an active region of the image sensor die and the light transmitting member. The image sensor package including a bonding material that couples the light transmitting member to the image sensor. The bonding material contacts a side of a pillar member, of the plurality of pillar members, that extends between a first end contacting the light transmitting member and a second end contacting the image sensor die.

    AN IMAGE SENSOR PACKAGE HAVING A LIGHT BLOCKING MEMBER

    公开(公告)号:US20200312897A1

    公开(公告)日:2020-10-01

    申请号:US16506497

    申请日:2019-07-09

    Abstract: According to an aspect, an image sensor package includes a substrate, an image sensor die coupled to the substrate, and a transparent member including a first surface and a second surface, where the second surface of the transparent member is coupled to the image sensor die via one or more dam members such that an empty space exists between an active area of the image sensor die and the second surface of the transparent member. The image sensor package includes a light blocking member coupled to or defined by the transparent member.

    IMAGE SENSOR SEMICONDUCTOR PACKAGES AND RELATED METHODS

    公开(公告)号:US20190229144A1

    公开(公告)日:2019-07-25

    申请号:US16374720

    申请日:2019-04-03

    Abstract: An image sensor semiconductor package (package) includes a printed circuit board (PCB) having a first surface and a second surface opposite the first surface. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die has a first surface with a photosensitive region and a second surface opposite the first surface of the CIS die. The second surface of the CIS die is coupled with the first surface of the PCB. A transparent cover is coupled over the photosensitive region of the CIS die. An image signal processor (ISP) is embedded within the PCB. One or more electrical couplers electrically couple the CIS die with the PCB. A plurality of electrical contacts on the second surface of the PCB are electrically coupled with the CIS die and with the ISP. The ISP is located between the plurality of electrical contacts of the second surface of the PCB and the CIS die.

    IMAGE SENSOR PACKAGE HAVING A LIGHT BLOCKING MEMBER

    公开(公告)号:US20230025520A1

    公开(公告)日:2023-01-26

    申请号:US17816797

    申请日:2022-08-02

    Abstract: According to an aspect, an image sensor package includes a substrate, an image sensor die coupled to the substrate, and a transparent member including a first surface and a second surface, where the second surface of the transparent member is coupled to the image sensor die via one or more dam members such that an empty space exists between an active area of the image sensor die and the second surface of the transparent member. The image sensor package includes a light blocking member coupled to or defined by the transparent member.

    MULTI-CHIP PACKAGING STRUCTURE FOR AN IMAGE SENSOR

    公开(公告)号:US20200058695A1

    公开(公告)日:2020-02-20

    申请号:US16103128

    申请日:2018-08-14

    Inventor: Yu-Te HSIEH

    Abstract: According to an aspect, a multi-chip packaging structure includes a first substrate having a first surface and a second surface, where the first substrate has a conductive layer portion. The multi-chip packaging structure includes an image sensor device coupled to the first surface of the first substrate, a first device coupled to the second surface of the first substrate, and a second substrate disposed apart from the first substrate, where the second substrate has a conductive layer portion. The conductive layer portion of the first substrate is communicatively connected to the conductive layer portion of the second substrate. The first device is disposed between the first substrate and the second substrate. The multi-chip packaging structure includes a second device coupled to the second substrate, and a third device coupled to the first substrate or the second substrate.

    HIGH RELIABILITY WAFER LEVEL SEMICONDUCTOR PACKAGING

    公开(公告)号:US20190229025A1

    公开(公告)日:2019-07-25

    申请号:US16374137

    申请日:2019-04-03

    Inventor: Yu-Te HSIEH

    Abstract: Implementations of semiconductor packages may include: a semiconductor wafer, a glass lid fixedly coupled to a first side of the semiconductor die by an adhesive, a redistribution layer coupled to a second side of the semiconductor die, and a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer coupled to the semiconductor die. The adhesive may be located in a trench around a perimeter of the semiconductor die and located in a corresponding trench around a perimeter of the glass lid.

    SEMICONDUCTOR DIE AND METHOD OF PACKAGING MULTI-DIE WITH IMAGE SENSOR

    公开(公告)号:US20180204866A1

    公开(公告)日:2018-07-19

    申请号:US15407224

    申请日:2017-01-16

    Inventor: Yu-Te HSIEH

    Abstract: A semiconductor wafer has an image sensor area with a light transmissive wafer, such as glass, disposed over the semiconductor wafer. A portion of the semiconductor wafer is removed to thin the wafer. A semiconductor die is disposed over a surface of the semiconductor wafer opposite the light transmissive wafer. An encapsulant is deposited around the semiconductor die. A portion of the encapsulant is removed to planarize the encapsulant. A conductive via is formed through the semiconductor wafer and first encapsulant. An interconnect structure is formed over the encapsulant and semiconductor die. The interconnect structure includes multiple insulating layers and multiple conductive layers. The multiple insulating layers can be an encapsulant. The semiconductor wafer is singulated to form a multi-die semiconductor package, which integrates the image sensor semiconductor die with other types of semiconductor die to enhance the image performance within the multi-die package.

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