- 专利标题： Low Leakage ReRAM FPGA Configuration Cell
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申请号： US15823216申请日： 2017-11-27
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公开(公告)号： US20180083634A1公开(公告)日： 2018-03-22
- 发明人: John L. McCollum , Esmat Z. Hamdy
- 申请人： Microsemi SoC Corp.
- 主分类号： H03K19/177
- IPC分类号： H03K19/177 ; H01L27/24 ; G11C13/00 ; H01L45/00
摘要：
A low-leakage resistive random access memory cell includes a complementary pair of bit lines and a switch node. A first ReRAM device is connected to a first one of the bit lines. A p-channel transistor has a source connected to the ReRAM device, a drain connected to the switch node, and a gate connected to a bias potential. A second ReRAM device is connected to a second one of the bit lines. An n-channel transistor has a source connected to the ReRAM device a drain connected to the switch node, and a gate connected to a bias potential.
公开/授权文献
- US10128852B2 Low leakage ReRAM FPGA configuration cell 公开/授权日：2018-11-13
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