Invention Application
- Patent Title: EXTENDED APPLICATION OF ERROR CHECKING AND CORRECTION CODE IN MEMORY
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Application No.: US15282793Application Date: 2016-09-30
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Publication No.: US20180095821A1Publication Date: 2018-04-05
- Inventor: Pete D. VOGT
- Applicant: Intel Corporation
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G11C11/4093

Abstract:
ECC (error checking and correction) can be extended to allow an ECC code to correct memory subarray errors. A memory device includes multiple input/output (I/O) connectors to interface with an external device such as a controller. The memory device includes multiple arrays or subarrays that are specifically mapped to I/O connectors instead of arbitrarily routed. As such, the data paths of the memory subarrays can be exclusively routed to a specific I/O connector. The I/O connector can be uniquely associated with a single memory subarray, or multiple memory subarrays can be mapped to a specific I/O connector. The mapping is in accordance with an error checking and correcting (ECC) code matrix, where a code of the ECC code matrix corresponding to the specific I/O connector is to check and correct data corruption errors and I/O errors for the associated one or multiple memory subarrays.
Public/Granted literature
- US10120749B2 Extended application of error checking and correction code in memory Public/Granted day:2018-11-06
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