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    EXTENDED PLATFORM WITH ADDITIONAL MEMORY MODULE SLOTS PER CPU SOCKET AND CONFIGURED FOR INCREASED PERFORMANCE
    4.
    发明申请
    EXTENDED PLATFORM WITH ADDITIONAL MEMORY MODULE SLOTS PER CPU SOCKET AND CONFIGURED FOR INCREASED PERFORMANCE 审中-公开

    公开(公告)号：US20180095909A1

    公开(公告)日：2018-04-05

    申请号：US15283186

    申请日：2016-09-30

    Applicant: INTEL CORPORATION

    Inventor： Bruce QUERBACH ,  Pete D. VOGT

    IPC: G06F13/16

    CPC classification number: G06F13/1678 ,  G06F1/18 ,  G06F13/1694 ,  G11C5/06

    Abstract: Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board (PCB) that includes a printed circuit board defining a length and a width, the length being greater than the width. The apparatus includes a first row of elements on thePCB, including a first memory region configured to receive at least one memory module. The apparatus includes a second row of elements on the PCB, including a first central processing unit (CPU) socket configured to receive a first CPU, and a second CPU socket configured to receive a second CPU, the first CPU socket and the second CPU socket positioned side by side along the width of the PCB. The apparatus also includes a third row of elements on the PCB, including a second memory region configured to receive a at least one memory module, wherein the second row of elements is positioned between the first row of elements and the third rows of elements. Other embodiments are described and claimed.

    EXTENDED PLATFORM WITH ADDITIONAL MEMORY MODULE SLOTS PER CPU SOCKET AND CONFIGURED FOR INCREASED PERFORMANCE
    5.
    发明申请
    EXTENDED PLATFORM WITH ADDITIONAL MEMORY MODULE SLOTS PER CPU SOCKET AND CONFIGURED FOR INCREASED PERFORMANCE 审中-公开

    公开(公告)号：US20190258594A1

    公开(公告)日：2019-08-22

    申请号：US16283597

    申请日：2019-02-22

    Applicant: Intel Corporation

    Inventor： Bruce QUERBACH ,  Pete D. VOGT

    IPC: G06F13/16 ,  G06F1/18

    Abstract: Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board (PCB) that includes a printed circuit board defining a length and a width, the length being greater than the width. The apparatus includes a first row of elements on the PCB, including a first memory region configured to receive at least one memory module. The apparatus includes a second row of elements on the PCB, including a first central processing unit (CPU) socket configured to receive a first CPU, and a second CPU socket configured to receive a second CPU, the first CPU socket and the second CPU socket positioned side by side along the width of the PCB. The apparatus also includes a third row of elements on the PCB, including a second memory region configured to receive a at least one memory module, wherein the second row of elements is positioned between the first row of elements and the third rows of elements. Other embodiments are described and claimed.

    EXTENDED APPLICATION OF ERROR CHECKING AND CORRECTION CODE IN MEMORY
    6.
    发明申请
    EXTENDED APPLICATION OF ERROR CHECKING AND CORRECTION CODE IN MEMORY 审中-公开

    公开(公告)号：US20180095821A1

    公开(公告)日：2018-04-05

    申请号：US15282793

    申请日：2016-09-30

    Applicant: Intel Corporation

    Inventor： Pete D. VOGT

    IPC: G06F11/10 ,  G11C11/4093

    CPC classification number: G06F11/1044 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4097

    Abstract: ECC (error checking and correction) can be extended to allow an ECC code to correct memory subarray errors. A memory device includes multiple input/output (I/O) connectors to interface with an external device such as a controller. The memory device includes multiple arrays or subarrays that are specifically mapped to I/O connectors instead of arbitrarily routed. As such, the data paths of the memory subarrays can be exclusively routed to a specific I/O connector. The I/O connector can be uniquely associated with a single memory subarray, or multiple memory subarrays can be mapped to a specific I/O connector. The mapping is in accordance with an error checking and correcting (ECC) code matrix, where a code of the ECC code matrix corresponding to the specific I/O connector is to check and correct data corruption errors and I/O errors for the associated one or multiple memory subarrays.

    STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS
    7.
    发明申请
    STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS 审中-公开

    公开(公告)号：US20190304953A1

    公开(公告)日：2019-10-03

    申请号：US16424355

    申请日：2019-05-28

    Applicant: Intel Corporation

    Inventor： Pete D. VOGT ,  Andre SCHAEFER ,  Warren MORROW ,  John B. HALBERT ,  Jin KIM ,  Kenneth D. SHOEMAKER

    IPC: H01L25/065 ,  H01L23/48 ,  G11C5/06 ,  H01L27/108

    Abstract: A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.

    REMOTE MEMORY OPERATIONS
    8.
    发明申请
    REMOTE MEMORY OPERATIONS 审中-公开

    公开(公告)号：US20180004687A1

    公开(公告)日：2018-01-04

    申请号：US15201373

    申请日：2016-07-01

    Applicant: Intel Corporation

    Inventor： Francesc GUIM BERNAT ,  Karthik KUMAR ,  Thomas WILLHALM ,  Narayan RANGANATHAN ,  Pete D. VOGT

    IPC: G06F13/16 ,  G06F13/42 ,  G06F13/40 ,  H04L29/08 ,  H04L12/803

    Abstract: An extension of node architecture and proxy requests enables a node to expose memory computation capability to remote nodes. A remote node can request execution of an operation by a remote memory computation resource, and the remote memory computation resource can execute the request locally and return the results of the computation. The node includes processing resources, a fabric interface, and a memory subsystem including a memory computation resource. The local execution of the request by the memory computation resource can reduce latency and bandwidth concerns typical with remote requests.

    READ DELIVERY FOR MEMORY SUBSYSTEM WITH NARROW BANDWIDTH REPEATER CHANNEL
    9.
    发明申请
    READ DELIVERY FOR MEMORY SUBSYSTEM WITH NARROW BANDWIDTH REPEATER CHANNEL 审中-公开

    公开(公告)号：US20170285941A1

    公开(公告)日：2017-10-05

    申请号：US15089455

    申请日：2016-04-01

    Applicant: Intel Corporation

    Inventor： Bill NALE ,  Pete D. VOGT

    IPC: G06F3/06

    CPC classification number: G06F13/16 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0631 ,  G06F3/0685 ,  G06F13/1678 ,  G06F13/4018 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10

    Abstract: A system includes a repeater architecture for reads where memory connects to a host for with one bandwidth, and repeats the channel with a lower bandwidth. A memory circuit includes a first group of read signal lines to couple point-to-point between a first group of memory devices and a host device. The memory circuit includes a second, smaller group of read signal lines to couple point-to-point between the first group of memory devices and a second group of memory devices, to extend the memory channel to the second group of memory devices. The memory circuit includes a repeater to share read bandwidth between the first and second groups of memory devices, with up to a portion of the bandwidth for reads to the second group of memory devices, and at least an amount equal to the bandwidth less the portion for reads to the first group of memory devices.

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