- 专利标题： HIGH-SPEED RECEIVER ARCHITECTURE
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申请号： US15839380申请日： 2017-12-12
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公开(公告)号： US20180102850A1公开(公告)日： 2018-04-12
- 发明人: Oscar Ernesto AGAZZI , Diego Ernesto CRIVELLI , Hugo Santiago CARRER , Mario Rafael HUEDA , German Cesar Augusto LUNA , Carl GRACE
- 申请人： INPHI CORPORATION
- 主分类号： H04B10/50
- IPC分类号： H04B10/50 ; H04B7/005 ; H04L25/02 ; H04B3/23 ; H03M13/41
摘要：
A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.
公开/授权文献
- US10097273B2 High-speed receiver architecture 公开/授权日：2018-10-09
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