- 专利标题： MULTIPROCESSOR CACHE BUFFER MANAGEMENT
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申请号： US15842920申请日： 2017-12-15
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公开(公告)号： US20180107617A1公开(公告)日： 2018-04-19
- 发明人: Ekaterina M. Ambroladze , Deanna P. Berger , Michael Fee , Arthur J. O'Neill, JR.
- 申请人： International Business Machines Corporation
- 主分类号： G06F13/16
- IPC分类号： G06F13/16 ; G06F13/42 ; G06F13/40
摘要：
In an approach for managing data transfer across a bus shared by processors, a request for a first set of data is received from a first processor. A request for a second set of data is received from a second processor. First portions of the first set of data and the second set of data are written to a buffer. Additional portions of each set of data are written to the buffer as portions are received. It is determined that a portion of the first set of data has a higher priority to the bus than a portion of the second set of data based on a priority scheme, wherein the priority scheme is based on return progress of each respective set of data having at least a portion of data in the buffer. The portion of the first set of data is granted access to the bus.
公开/授权文献
- US10169260B2 Multiprocessor cache buffer management 公开/授权日：2019-01-01
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