发明申请
- 专利标题: OFFSTATE PARASITIC LEAKAGE REDUCTION FOR TUNNELING FIELD EFFECT TRANSISTORS
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申请号: US15576468申请日: 2015-06-27
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公开(公告)号: US20180158933A1公开(公告)日: 2018-06-07
- 发明人: Van H. LE , Gilbert DEWEY , Benjamin CHU-KUNG , Ashish AGRAWAL , Matthew V. METZ , Willy RACHMADY , Marc C. FRENCH , Jack T. KAVALIEROS , Rafael RIOS , Seiyon KIM , Seung Hoon SUNG , Sanaz K. GARDNER , James M. POWERS , Sherry R. TAFT
- 申请人: Intel Corporation
- 国际申请: PCT/US2015/038192 WO 20150627
- 主分类号: H01L29/66
- IPC分类号: H01L29/66 ; H01L29/786
摘要:
A method including forming a non-planar conducting channel of a device between junction regions on a substrate, the substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. A method including forming a buffer material on a semiconductor substrate, the buffer material including a semiconductor material including a different lattice structure than the substrate; forming a blocking material on the buffer material, the blocking material including a property to inhibit carrier leakage; and forming a transistor device on the substrate. An apparatus including a non-planar multi-gate device on a substrate including a transistor device including a channel disposed on a substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage.
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