公开(公告)号：US20230377947A1

公开(公告)日：2023-11-23

申请号：US18356780

申请日：2023-07-21

Applicant: Intel Corporation

Inventor： Cheng-Ying HUANG ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Aaron LILAK ,  Ehren MANNEBACH ,  Patrick MORROW ,  Anh PHAN ,  Willy RACHMADY ,  Hui Jae YOO

IPC: H01L21/762 ,  H01L21/225 ,  H01L21/265 ,  H01L21/02 ,  H01L29/78 ,  H01L29/06 ,  H01L21/311 ,  H01L21/266

CPC classification number: H01L21/76264 ,  H01L21/2253 ,  H01L21/2255 ,  H01L21/26533 ,  H01L21/02236 ,  H01L21/02252 ,  H01L29/7853 ,  H01L29/0649 ,  H01L21/31111 ,  H01L21/76267 ,  H01L21/02255 ,  H01L21/266

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.

公开(公告)号：US20220310600A1

公开(公告)日：2022-09-29

申请号：US17842450

申请日：2022-06-16

Applicant: Intel Corporation

Inventor： Cory E. WEBER ,  Harold W. KENNEL ,  Willy RACHMADY ,  Gilbert DEWEY

IPC: H01L27/092 ,  H01L21/8258 ,  H01L27/12 ,  H01L21/02 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8238

Abstract: Semiconductor nanowire devices having (111)-plane channel sidewalls and methods of fabricating semiconductor nanowire devices having (111)-plane channel sidewalls are described. For example, an integrated circuit structure includes a first semiconductor device including a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires comprising a discrete channel region having lateral sidewalls along a carrier transport direction. The integrated circuit structure also includes a second semiconductor device including a semiconductor fin disposed above the substrate, the semiconductor fin having a channel region with a top and side surfaces, the channel region having lateral sidewalls along a carrier transport direction.

公开(公告)号：US20210296180A1

公开(公告)日：2021-09-23

申请号：US17336565

申请日：2021-06-02

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Matthew V. METZ ,  Willy RACHMADY ,  Anand S. MURTHY ,  Chandra S. MOHAPATRA ,  Tahir GHANI ,  Sean T. MA ,  Jack T. KAVALIEROS

IPC: H01L21/8234 ,  H01L21/02

Abstract: An apparatus is described. The apparatus includes a FINFET device having a channel. The channel is composed of a first semiconductor material that is epitaxially grown on a subfin structure beneath the channel. The subfin structure is composed of a second semiconductor material that is different than the first semiconductor material. The subfin structure is epitaxially grown on a substrate composed of a third semiconductor material that is different than the first and second semiconductor materials. The subfin structure has a doped region to substantially impede leakage currents between the channel and the substrate.

公开(公告)号：US20200312841A1

公开(公告)日：2020-10-01

申请号：US16367175

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Cheng-Ying HUANG ,  Gilbert DEWEY ,  Jack KAVALIEROS ,  Caleb BARRETT ,  Jay P. GUPTA ,  Nishant GUPTA ,  Kaiwen HSU ,  Byungki JUNG ,  Aravind S. KILLAMPALLI ,  Justin RAILSBACK ,  Supanee SUKRITTANON ,  Prashant WADHWA

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/02

Abstract: Transistor structures including a non-planar body that has an active portion comprising a semiconductor material of a first height that is variable, and an inactive portion comprising an oxide of the semiconductor material of a second variable height, complementary to the first height. Gate electrodes and source/drain terminals may be coupled through a transistor channel having any width that varies according to the first height. Oxidation of a semiconductor material may be selectively catalyzed to convert a desired portion of a non-planar body into the oxide of the semiconductor material. Oxidation may be enhanced through the application of a catalyst, such as one comprising metal and oxygen, for example.

公开(公告)号：US20200287036A1

公开(公告)日：2020-09-10

申请号：US16645758

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Cheng-Ying HUANG ,  Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Sean T. MA ,  Jack T. KAVALIEROS

IPC: H01L29/778 ,  H01L29/08 ,  H01L29/205 ,  H01L29/15 ,  H01L21/02 ,  H01L29/66

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate, and a channel area above the substrate and including a first III-V material. A source area may be above the substrate and including a second III-V material. An interface between the channel area and the source area may include the first III-V material. The source area may include a barrier layer of a third III-V material above the substrate. A current is to flow between the source area and the channel area through the barrier layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20200212038A1

公开(公告)日：2020-07-02

申请号：US16236113

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Aaron LILAK ,  Brennen MUELLER ,  Hui Jae YOO ,  Patrick MORROW ,  Anh PHAN ,  Cheng-Ying HUANG ,  Ehren MANNEBACH ,  Kimin JUN ,  Gilbert DEWEY

IPC: H01L27/092 ,  H01L29/16 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8238

Abstract: An integrated circuit structure comprises a substrate and a stacked channel of self-aligned heterogeneous materials, wherein the stacked channel of self-aligned heterogeneous materials comprises an NMOS channel material over the substrate; and a PMOS channel material stacked over and self-aligned with the NMOS channel material. A heterogeneous gate stack is in contact the both the NMOS channel material and the PMOS channel material.

公开(公告)号：US20200161473A1

公开(公告)日：2020-05-21

申请号：US16633094

申请日：2017-09-17

Applicant: Intel Corporation

Inventor： Prashant MAJHI ,  Willy RACHMADY ,  Brian S. DOYLE ,  Abhishek A. SHARMA ,  Elijah V. KARPOV ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66

Abstract: Strained thin film transistors are described. In an example, an integrated circuit structure includes a strain inducing layer on an insulator layer above a substrate. A polycrystalline channel material layer is on the strain inducing layer. A gate dielectric layer is on a first portion of the polycrystalline channel material. A gate electrode is on the gate dielectric layer, the gate electrode having a first side opposite a second side. A first conductive contact is adjacent the first side of the gate electrode, the first conductive contact on a second portion of the polycrystalline channel material. A second conductive contact adjacent the second side of the gate electrode, the second conductive contact on a third portion of the polycrystalline channel material.

公开(公告)号：US20200066843A1

公开(公告)日：2020-02-27

申请号：US16612259

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Sean T. MA ,  Gilbert DEWEY ,  Willy RACHMADY ,  Matthew V. METZ ,  Cheng-Ying HUANG ,  Harold W. KENNEL ,  Jack T. KAVALIEROS ,  Anand S. MURTHY ,  Tahir GHANI

IPC: H01L29/10 ,  H01L29/205 ,  H01L29/78 ,  H01L29/775 ,  H01L29/66

Abstract: An electronic device comprises a channel layer on a buffer layer on a substrate. The channel layer has a first portion and a second portion adjacent to the first portion. The first portion comprises a first semiconductor. The second portion comprises a second semiconductor that has a bandgap greater than a bandgap of the first semiconductor.

公开(公告)号：US20190189770A1

公开(公告)日：2019-06-20

申请号：US16284980

申请日：2019-02-25

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Matthew V. METZ ,  Van H. LE ,  Jack T. KAVALIEROS ,  Sanaz K. GARDNER

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/78 ,  H01L29/06 ,  H01L29/775 ,  H01L29/423 ,  B82Y10/00 ,  H01L27/092 ,  H01L29/16 ,  H01L29/08

CPC classification number: H01L29/6681 ,  B82Y10/00 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/30612 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/20 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/78696

Abstract: An apparatus including a three-dimensional semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the three-dimensional semiconductor body including a plurality of nanowires including a germanium material disposed in respective planes separated in the junction regions by a second material, wherein a lattice constant of the second material is similar to a lattice constant of the germanium material; and a gate stack disposed on the channel region, the gate stack including a gate electrode disposed on a gate dielectric. A method of including forming a plurality of nanowires in separate planes on a substrate, each of the plurality of nanowires including a germanium material and separated from an adjacent nanowire by a sacrificial material; disposing a gate stack on the plurality of nanowires in a designated channel region, the gate stack including a dielectric material and a gate electrode.

公开(公告)号：US20190122972A1

公开(公告)日：2019-04-25

申请号：US16094817

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Benjamin CHU-KUNG ,  Van H. LE ,  Willy RACHMADY ,  Matthew V. METZ ,  Jack T. KAVALIEROS ,  Ashish AGRAWAL ,  Seung Hoon SUNG

IPC: H01L23/498 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: A subfin layer is deposited on a substrate. A fin layer is deposited on the subfin layer. The subfin layer has a conduction band energy offset relative to the fin layer to prevent a leakage in the subfin layer. In one embodiment, the subfin layer comprises a group IV semiconductor material layer that has a bandgap greater than a bandgap of the fin layer.