公开(公告)号：US20200321446A1

公开(公告)日：2020-10-08

申请号：US16635739

申请日：2017-09-28

申请人： Intel Corporation

发明人： Seiyon KIM ,  Uygar E. AVCI ,  Joshua M. HOWARD ,  Ian A. YOUNG ,  Daniel H. MORRIS

IPC分类号： H01L29/66 ,  H01L29/51

摘要： Field effect transistors having a ferroelectric or antiferroelectric gate dielectric structure are described. In an example, an integrated circuit structure includes a semiconductor channel structure includes a monocrystalline material. A gate dielectric is over the semiconductor channel structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer. A gate electrode has a conductive layer on the ferroelectric or antiferroelectric polycrystalline material layer, the conductive layer including a metal. A first source or drain structure is at a first side of the gate electrode. A second source or drain structure is at a second side

公开(公告)号：US20200185526A1

公开(公告)日：2020-06-11

申请号：US16785975

申请日：2020-02-10

申请人： Intel Corporation

发明人： Seiyon KIM ,  Rafael RIOS ,  Fahmida FERDOUSI ,  Kelin J. KUHN

IPC分类号： H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L21/306 ,  H01L21/02 ,  H01L29/423 ,  H01L29/16 ,  H01L29/775 ,  B82Y40/00 ,  B82Y10/00

摘要： Non-planar semiconductor devices having hybrid geometry-based active regions are described. For example, a semiconductor device includes a hybrid channel region including a nanowire portion disposed above an omega-FET portion disposed above a fin-FET portion. A gate stack is disposed on exposed surfaces of the hybrid channel region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the hybrid channel region.

公开(公告)号：US20180204932A1

公开(公告)日：2018-07-19

申请号：US15570965

申请日：2015-06-17

申请人： Intel Corporation

发明人： Rishabh MEHANDRU ,  Partick MORROW ,  Ranjith KUMAR ,  Cory E. WEBER ,  Seiyon KIM ,  Stephen M. CEA ,  Tahir GHANI

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L27/108

CPC分类号： H01L29/66795 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/10826 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/78 ,  H01L29/785

摘要： Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

公开(公告)号：US20180158933A1

公开(公告)日：2018-06-07

申请号：US15576468

申请日：2015-06-27

申请人： Intel Corporation

发明人： Van H. LE ,  Gilbert DEWEY ,  Benjamin CHU-KUNG ,  Ashish AGRAWAL ,  Matthew V. METZ ,  Willy RACHMADY ,  Marc C. FRENCH ,  Jack T. KAVALIEROS ,  Rafael RIOS ,  Seiyon KIM ,  Seung Hoon SUNG ,  Sanaz K. GARDNER ,  James M. POWERS ,  Sherry R. TAFT

IPC分类号： H01L29/66 ,  H01L29/786

CPC分类号： H01L29/66977 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78609 ,  H01L29/78684 ,  H01L29/78696

摘要： A method including forming a non-planar conducting channel of a device between junction regions on a substrate, the substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. A method including forming a buffer material on a semiconductor substrate, the buffer material including a semiconductor material including a different lattice structure than the substrate; forming a blocking material on the buffer material, the blocking material including a property to inhibit carrier leakage; and forming a transistor device on the substrate. An apparatus including a non-planar multi-gate device on a substrate including a transistor device including a channel disposed on a substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage.

公开(公告)号：US20180151702A1

公开(公告)日：2018-05-31

申请号：US15576251

申请日：2015-06-27

申请人： Intel Corporation

发明人： Seiyon KIM ,  Gopinath BHIMARASETTI ,  Rafael RIOS ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Anand S. MURTHY ,  Rishabh MEHANDRU

IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/02233 ,  H01L21/02546 ,  H01L23/49827 ,  H01L23/49838 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

摘要： A method including forming a non-planar conducting channel of a multi-gate device on a substrate, the channel including a height dimension defined from a base at a surface of the substrate; modifying less than an entire portion of the channel; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. An apparatus including a non-planar multi-gate device on a substrate including a channel including a height dimension defining a conducting portion and an oxidized portion and a gate stack disposed on the channel, the gate stack including a dielectric material and a gate electrode.

公开(公告)号：US20200152738A1

公开(公告)日：2020-05-14

申请号：US16740132

申请日：2020-01-10

申请人： Intel Corporation

发明人： Seiyon KIM ,  Kelin J. KUHN ,  Tahir GHANI ,  Anand S. MURTHY ,  Mark ARMSTRONG ,  Rafael RIOS ,  Abhijit Jayant PETHE ,  Willy RACHMADY

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L21/3115 ,  H01L21/3105 ,  H01L21/306 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786

摘要： A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

公开(公告)号：US20190051725A1

公开(公告)日：2019-02-14

申请号：US16153456

申请日：2018-10-05

申请人： Intel Corporation

发明人： Seiyon KIM ,  Kelin J. KUHN ,  Tahir GHANI ,  Anand S. MURTHY ,  Mark ARMSTRONG ,  Rafael RIOS ,  Abhijit Jayant PETHE ,  Willy RACHMADY

IPC分类号： H01L29/06 ,  H01L29/423

摘要： A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

公开(公告)号：US20170358658A1

公开(公告)日：2017-12-14

申请号：US15506205

申请日：2014-09-26

申请人： INTEL CORPORATION

发明人： Rafael RIOS ,  Kelin J. KUHN ,  Seiyon KIM ,  Justin R. Weber

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/423

CPC分类号： H01L29/66439 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/122 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/775 ,  H01L29/778 ,  H01L29/78636 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696 ,  H01L49/00

摘要： Embodiments of the invention include metal oxide metal field effect transistors (MOMFETs) and methods of making such devices. In embodiments, the MOMFET device includes a source and a drain with a channel disposed between the source and the drain. According to an embodiment, the channel has at least one confined dimension that produces a quantum confinement effect in the channel. In an embodiment, the MOMFET device also includes a gate electrode that is separated from the channel by a gate dielectric. According to embodiments, the band-gap energy of the channel may be modulated by changing the size of the channel, the material used for the channel, and/or the surface termination applied to the channel. Embodiments also include forming an type device and a P-type device by controlling the work-function of the source and drain relative to the conduction band and valance band energies of the channel.

公开(公告)号：US20170162676A1

公开(公告)日：2017-06-08

申请号：US15434981

申请日：2017-02-16

申请人： Intel Corporation

发明人： Annalisa CAPPELLANI ,  Stephen M. CEA ,  Tahir GHANI ,  Harry GOMEZ ,  Jack T. KAVALIEROS ,  Patrick H. KEYS ,  Seiyon KIM ,  Kelin J. KUHN ,  Aaron D. LILAK ,  Rafael RIOS ,  Mayank SAHNI

IPC分类号： H01L29/66 ,  H01L21/762 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L29/66818 ,  B82Y10/00 ,  H01L21/762 ,  H01L21/76216 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

摘要： Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.

公开(公告)号：US20170158501A1

公开(公告)日：2017-06-08

申请号：US15301337

申请日：2014-06-27

申请人： Intel Corporation

发明人： Jorge A. MUNOZ ,  Dmitri E. NIKONOV ,  Kelin J. KUHN ,  Patrick THEOFANIS ,  Chytra PAWASHE ,  Kevin LIN ,  Seiyon KIM

IPC分类号： B82B1/00 ,  H01H59/00 ,  B82B3/00 ,  H01L29/66 ,  H01L29/84 ,  H01L29/82

CPC分类号： B82B1/005 ,  B81B3/0016 ,  B81B7/02 ,  B81B2201/014 ,  B81B2203/0118 ,  B82B1/002 ,  B82B3/0023 ,  B82Y15/00 ,  B82Y25/00 ,  B82Y40/00 ,  H01H1/0094 ,  H01H1/54 ,  H01H59/0009 ,  H01L29/66227 ,  H01L29/82 ,  H01L29/84 ,  Y10S977/732 ,  Y10S977/838 ,  Y10S977/888 ,  Y10S977/938

摘要： Nanoelectromechanical (NEMS) devices having nanomagnets for an improved range of operating voltages and improved control of dimensions of a cantilever are described. For example, in an embodiment, a nanoelectromechanical (NEMS) device includes a substrate layer, a first magnetic layer disposed above the substrate layer, a first dielectric layer disposed above the first magnetic layer, a second dielectric disposed above the first dielectric layer, and a cantilever disposed above the second dielectric layer. The cantilever bends from a first position to a second position towards the substrate layer when a voltage is applied to the cantilever.