- 专利标题: GRAPH PARTITIONING AND PLACEMENT FOR MULTI-CHIP NEUROSYNAPTIC NETWORKS
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申请号: US15457658申请日: 2017-03-13
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公开(公告)号: US20180260682A1公开(公告)日: 2018-09-13
- 发明人: Arnon Amir , Pallab Datta , Myron D. Flickner , Dharmendra S. Modha , Tapan K. Nayak
- 申请人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 主分类号: G06N3/04
- IPC分类号: G06N3/04
摘要:
Graph partitioning and placement for multi-chip neurosynaptic networks. According to various embodiments, a neural network description is read. The neural network description describes a plurality of neurons. The plurality of neurons has a mapping from an input domain of the neural network. The plurality of neurons is labeled based on the mapping from the input domain. The plurality of neurons is grouped into a plurality of groups according to the labeling. Each of the plurality of groups is continuous within the input domain. Each of the plurality of groups is assigned to at least one neurosynaptic core.
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