- 专利标题: METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AS A GETTERING LAYER
-
申请号: US15980902申请日: 2018-05-16
-
公开(公告)号: US20180337064A1公开(公告)日: 2018-11-22
- 发明人: HIDEKI TAKEUCHI
- 申请人: Atomera Incorporated
- 主分类号: H01L21/322
- IPC分类号: H01L21/322 ; H01L23/48 ; H01L21/02 ; H01L21/768
摘要:
A semiconductor processing method may include forming a superlattice gettering layer on a front side of a semiconductor substrate having a first thickness, epitaxially growing an active semiconductor layer on the superlattice gettering layer opposite the semiconductor substrate, forming at least one semiconductor device in the active semiconductor layer, and forming at least one metal interconnect layer on the active layer, and at least one metal through-via extending from the at least one metal interconnect layer into the semiconductor substrate. The method may further include thinning the semiconductor substrate from a back side thereof to a second thickness less than the first thickness, and thinning the semiconductor substrate. The superlattice gettering layer getters metal ions released by the forming of the at least one metal interconnect layer and at least one metal through-via, and thinning the substrate.
公开/授权文献
信息查询
IPC分类: