公开(公告)号：US20230136797A1

公开(公告)日：2023-05-04

申请号：US17452604

申请日：2021-10-28

申请人： Atomera Incorporated

发明人： MAREK HYTHA ,  KEITH DORAN WEEKS ,  NYLES WYNN CODY

IPC分类号： H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/66

摘要： A method for making a semiconductor device may include forming a superlattice above a semiconductor layer, the superlattice including a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include selectively etching the superlattice to remove semiconductor atoms and cause non-semiconductor atoms to accumulate adjacent the semiconductor layer, epitaxially growing an active semiconductor device layer above the semiconductor layer and accumulated non-semiconductor atoms after the selective etching, and forming at least one circuit in the epitaxially grown active semiconductor device layer.

公开(公告)号：US20230122723A1

公开(公告)日：2023-04-20

申请号：US18069287

申请日：2022-12-21

申请人： Atomera Incorporated

发明人： KEITH DORAN WEEKS ,  NYLES WYNN CODY ,  MAREK HYTHA ,  ROBERT J. MEARS ,  ROBERT JOHN STEPHENSON ,  HIDEKI TAKEUCHI

IPC分类号： H01L29/15 ,  H01L29/66 ,  H01L29/78

摘要： A method for making a semiconductor gate-all-around (GAA) device may include forming source and drain regions on a semiconductor substrate, forming a plurality of semiconductor nanostructures extending between the source and drain regions, and forming a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement. Furthermore, the method may include forming at least one superlattice may be within at least one of the nanostructures. The at least one superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

公开(公告)号：US20220384612A1

公开(公告)日：2022-12-01

申请号：US17330860

申请日：2021-05-26

申请人： Atomera Incorporated

发明人： MAREK HYTHA ,  Nyles Wynn Cody ,  Keith Doran Weeks

IPC分类号： H01L29/66 ,  H01L29/15

摘要： A method for making a semiconductor device may include forming a semiconductor layer, and forming a superlattice adjacent the semiconductor layer and including stacked groups of layers. Each group of layers may include stacked base semiconductor monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one oxygen monolayer of a given group of layers may comprise an atomic percentage of 18O greater than 10 percent.

公开(公告)号：US20220367676A1

公开(公告)日：2022-11-17

申请号：US17873426

申请日：2022-07-26

申请人： ATOMERA INCORPORATED

发明人： RICHARD BURTON

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L29/732 ,  H01L29/15 ,  H01L29/10

摘要： A bipolar junction transistor (BJT) may include a substrate defining a collector region therein. A first superlattice may be on the substrate including a plurality of stacked groups of first layers, with each group of first layers including a first plurality of stacked base semiconductor monolayers defining a first base semiconductor portion, and at least one first non-semiconductor monolayer constrained within a crystal lattice of adjacent first base semiconductor portions. Furthermore, a base may be on the first superlattice, and a second superlattice may be on the base including a second plurality of stacked groups of second layers, with each group of second layers including a plurality of stacked base semiconductor monolayers defining a second base semiconductor portion, and at least one second non-semiconductor monolayer constrained within a crystal lattice of adjacent second base semiconductor portions. An emitter may be on the second superlattice.

公开(公告)号：US20220367675A1

公开(公告)日：2022-11-17

申请号：US17873411

申请日：2022-07-26

申请人： ATOMERA INCORPORATED

发明人： RICHARD BURTON

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L29/732 ,  H01L29/15 ,  H01L29/10

摘要： A method for making a bipolar junction transistor (BJT) may include forming a first superlattice on a substrate defining a collector region therein. The first superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a base on the first superlattice, and forming a second superlattice on the base comprising a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming an emitter on the second superlattice.

公开(公告)号：US20220344155A1

公开(公告)日：2022-10-27

申请号：US17236289

申请日：2021-04-21

申请人： Atomera Incorporated

发明人： MAREK HYTHA ,  KEITH DORAN WEEKS ,  NYLES WYNN CODY ,  HIDEKI TAKEUCHI

IPC分类号： H01L21/02 ,  H01L21/8234

摘要： A method for making a semiconductor device may include forming a first single crystal silicon layer having a first percentage of silicon 28, and forming a superlattice above the first single crystal silicon layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The method may further include forming a second single crystal silicon layer above the superlattice having a second percentage of silicon 28 higher than the first percentage of silicon 28.

公开(公告)号：US20210391426A1

公开(公告)日：2021-12-16

申请号：US16898589

申请日：2020-06-11

申请人： Atomera Incorporated

发明人： HIDEKI TAKEUCHI ,  Yung-Hsuan Yang

IPC分类号： H01L29/15 ,  H01L29/267 ,  H01L29/423 ,  H01L29/10

摘要： A semiconductor device may include a semiconductor substrate, and shallow trench isolation (STI) regions in the semiconductor substrate defining an active region therebetween in the semiconductor substrate, with the active region having rounded shoulders adjacent the STI regions with an interior angle of at least 125°. The semiconductor device may further include a superlattice on the active region including stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may also include a semiconductor circuit on the substrate including the superlattice.

公开(公告)号：US11183565B2

公开(公告)日：2021-11-23

申请号：US16513825

申请日：2019-07-17

申请人： ATOMERA INCORPORATED

发明人： Richard Burton ,  Marek Hytha ,  Robert J. Mears

IPC分类号： H01L29/06 ,  H01L31/00 ,  H01L29/15 ,  H01L29/16 ,  H01L29/80 ,  H01L29/66 ,  H01L29/93 ,  H01L29/78

摘要： A semiconductor device may include a substrate and a hyper-abrupt junction region carried by the substrate. The hyper-abrupt region may include a first semiconductor layer having a first conductivity type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer and having a second conductivity type different than the first conductivity type, and a second superlattice layer on the second semiconductor layer. The semiconductor device may further include a gate dielectric layer on the second superlattice layer of the hyper-abrupt junction region, a gate electrode on the gate dielectric layer, and spaced apart source and drain regions adjacent the hyper-abrupt junction region.

公开(公告)号：US10854717B2

公开(公告)日：2020-12-01

申请号：US16192923

申请日：2018-11-16

申请人： ATOMERA INCORPORATED

发明人： Hideki Takeuchi ,  Daniel Connelly ,  Marek Hytha ,  Richard Burton ,  Robert J. Mears

IPC分类号： H01L29/15 ,  H01L29/08 ,  H01L29/66 ,  H01L21/225 ,  H01L21/283 ,  H01L29/78 ,  H01L29/45 ,  H01L21/265

摘要： A method for making a FINFET may include forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice, with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region.

公开(公告)号：US20200343367A1

公开(公告)日：2020-10-29

申请号：US16853884

申请日：2020-04-21

申请人： ATOMERA INCORPORATED

发明人： HIDEKI TAKEUCHI ,  Richard Burton ,  Yung-Hsuan Yang

IPC分类号： H01L29/66 ,  H01L29/15 ,  H01L29/78

摘要： A method for making a semiconductor device may include forming spaced apart first and second doped regions in a substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The method may further include forming a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming a gate overlying the asymmetric channel.