公开(公告)号：US20230122723A1

公开(公告)日：2023-04-20

申请号：US18069287

申请日：2022-12-21

申请人： Atomera Incorporated

发明人： KEITH DORAN WEEKS ,  NYLES WYNN CODY ,  MAREK HYTHA ,  ROBERT J. MEARS ,  ROBERT JOHN STEPHENSON ,  HIDEKI TAKEUCHI

IPC分类号： H01L29/15 ,  H01L29/66 ,  H01L29/78

摘要： A method for making a semiconductor gate-all-around (GAA) device may include forming source and drain regions on a semiconductor substrate, forming a plurality of semiconductor nanostructures extending between the source and drain regions, and forming a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement. Furthermore, the method may include forming at least one superlattice may be within at least one of the nanostructures. The at least one superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

公开(公告)号：US20220344155A1

公开(公告)日：2022-10-27

申请号：US17236289

申请日：2021-04-21

申请人： Atomera Incorporated

发明人： MAREK HYTHA ,  KEITH DORAN WEEKS ,  NYLES WYNN CODY ,  HIDEKI TAKEUCHI

IPC分类号： H01L21/02 ,  H01L21/8234

摘要： A method for making a semiconductor device may include forming a first single crystal silicon layer having a first percentage of silicon 28, and forming a superlattice above the first single crystal silicon layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The method may further include forming a second single crystal silicon layer above the superlattice having a second percentage of silicon 28 higher than the first percentage of silicon 28.

公开(公告)号：US20210391426A1

公开(公告)日：2021-12-16

申请号：US16898589

申请日：2020-06-11

申请人： Atomera Incorporated

发明人： HIDEKI TAKEUCHI ,  Yung-Hsuan Yang

IPC分类号： H01L29/15 ,  H01L29/267 ,  H01L29/423 ,  H01L29/10

摘要： A semiconductor device may include a semiconductor substrate, and shallow trench isolation (STI) regions in the semiconductor substrate defining an active region therebetween in the semiconductor substrate, with the active region having rounded shoulders adjacent the STI regions with an interior angle of at least 125°. The semiconductor device may further include a superlattice on the active region including stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may also include a semiconductor circuit on the substrate including the superlattice.

公开(公告)号：US20200343367A1

公开(公告)日：2020-10-29

申请号：US16853884

申请日：2020-04-21

申请人： ATOMERA INCORPORATED

发明人： HIDEKI TAKEUCHI ,  Richard Burton ,  Yung-Hsuan Yang

IPC分类号： H01L29/66 ,  H01L29/15 ,  H01L29/78

摘要： A method for making a semiconductor device may include forming spaced apart first and second doped regions in a substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The method may further include forming a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming a gate overlying the asymmetric channel.

公开(公告)号：US20200161425A1

公开(公告)日：2020-05-21

申请号：US16193000

申请日：2018-11-16

申请人： ATOMERA INCORPORATED

发明人： HIDEKI TAKEUCHI ,  Daniel Connelly ,  Marek Hytha ,  Richard Burton ,  Robert J. Mears

IPC分类号： H01L29/15 ,  H01L29/66 ,  H01L29/165 ,  H01L29/10

摘要： A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween, and forming a gate on the channel region. The method may further include forming a body contact in the semiconductor layer and including a body contact dopant diffusion blocking superlattice extending through the body contact to divide the body contact into a first body contact region and an second body contact region with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region. The body contact dopant diffusion blocking superlattice may include a respective plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

公开(公告)号：US20180040724A1

公开(公告)日：2018-02-08

申请号：US15670231

申请日：2017-08-07

申请人： ATOMERA INCORPORATED

发明人： ROBERT J. MEARS ,  HIDEKI TAKEUCHI ,  MAREK HYTHA

IPC分类号： H01L29/737 ,  H01L27/092 ,  H01L29/78 ,  H01L29/161 ,  H01L29/66 ,  H01L29/15 ,  H01L29/10

摘要： A semiconductor device may include at least one double-barrier resonant tunneling diode (DBRTD). The at least one DBRTD may include a first doped semiconductor layer and a first barrier layer on the first doped semiconductor layer and including a superlattice. The superlattice may include stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one DBRTD may further include an intrinsic semiconductor layer on the first barrier layer, a second barrier layer on the intrinsic semiconductor layer, and a second doped semiconductor layer on the second superlattice layer.

公开(公告)号：US20220005926A1

公开(公告)日：2022-01-06

申请号：US17305098

申请日：2021-06-30

申请人： Atomera Incorporated

发明人： KEITH DORAN WEEKS ,  NYLES WYNN CODY ,  MAREK HYTHA ,  ROBERT J. MEARS ,  ROBERT JOHN STEPHENSON ,  HIDEKI TAKEUCHI

IPC分类号： H01L29/15 ,  H01L29/78

摘要： A semiconductor device may include a semiconductor layer and a superlattice adjacent the semiconductor layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one non-semiconductor monolayer in a first group of layers of the superlattice may comprise oxygen and be devoid of carbon, and the at least one non-semiconductor monolayer in a second group of layers of the superlattice may comprise carbon.

公开(公告)号：US20200161429A1

公开(公告)日：2020-05-21

申请号：US16192987

申请日：2018-11-16

申请人： ATOMERA INCORPORATED

发明人： HIDEKI TAKEUCHI ,  DANIEL CONNELLY ,  MAREK HYTHA ,  RICHARD BURTON ,  ROBERT J. MEARS

IPC分类号： H01L29/15 ,  H01L29/08 ,  H01L29/66 ,  H01L29/165 ,  H01L21/265 ,  H01L29/167 ,  H01L21/225

摘要： A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region.

公开(公告)号：US20190189665A1

公开(公告)日：2019-06-20

申请号：US15843017

申请日：2017-12-15

申请人： ATOMERA INCORPORATED

发明人： YI-ANN CHEN ,  ABID HUSAIN ,  HIDEKI TAKEUCHI

IPC分类号： H01L27/146 ,  H01L29/15 ,  H01L29/10 ,  H01L29/16

CPC分类号： H01L27/14634 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/14689 ,  H01L27/1469 ,  H01L29/1033 ,  H01L29/152 ,  H01L29/16

摘要： A CMOS image sensor may include a first semiconductor chip including an array of image sensor pixels and readout circuitry electrically connected thereto, and a second semiconductor chip coupled to the first semiconductor chip in a stack and including image processing circuitry electrically connected to the readout circuitry. The readout circuitry may include a plurality of transistors each including spaced apart source and drain regions, a superlattice channel extending between the source and drain regions, and a gate including a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.

公开(公告)号：US20190189657A1

公开(公告)日：2019-06-20

申请号：US15842981

申请日：2017-12-15

申请人： ATOMERA INCORPORATED

发明人： YI-ANN CHEN ,  ABID HUSAIN ,  HIDEKI TAKEUCHI

IPC分类号： H01L27/146

CPC分类号： H01L27/14616 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14689 ,  H01L27/1469 ,  H01L29/152

摘要： A method for making a CMOS image sensor may include forming a first semiconductor chip including an array of image sensor pixels and readout circuitry electrically connected thereto, forming a second semiconductor chip including image processing circuitry electrically connected to the readout circuitry, and coupling the first semiconductor chip and the second semiconductor chip in a stack. The processing circuitry may include a plurality of transistors each including spaced apart source and drain regions, a superlattice channel extending between the source and drain regions, and a gate including a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.