Invention Application
- Patent Title: METHODS AND APPARATUS FOR HANDLING RUNTIME MEMORY DEPENDENCIES
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Application No.: US15637637Application Date: 2017-06-29
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Publication No.: US20190004804A1Publication Date: 2019-01-03
- Inventor: Andrei Mihai Hagiescu Miriste , Byron Sinclair , Joseph Garvey
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F9/38
- IPC: G06F9/38 ; G06F9/48 ; G06F9/30

Abstract:
An integrated circuit may include elastic datapaths or pipelines, through which software threads or iterations of loops, may be executed. Throttling circuitry may be coupled along an elastic pipeline in the integrated circuit. The throttling circuitry may include dependency detection circuitry that dynamically detect memory dependency issues that may arise during runtime. To mitigate these dependency issues, the throttling circuitry may assert stall signals to upstream stages in the pipeline.Additionally, the throttling circuitry may control the pipeline to resolve a store operation prior to a corresponding load operation in order to avoid store/load conflicts. In an embodiment, the throttling circuitry may include a validator circuit, a rewind block, a revert block, and a flush block. The throttling circuitry may pass speculative iterations through the rewind block, and later validate the speculative iterations using the validator block.
Public/Granted literature
- US11379242B2 Methods and apparatus for using load and store addresses to resolve memory dependencies Public/Granted day:2022-07-05
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