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    METHODS AND APPARATUS FOR PROFILE-GUIDED OPTIMIZATION OF INTEGRATED CIRCUITS
    2.
    发明申请
    METHODS AND APPARATUS FOR PROFILE-GUIDED OPTIMIZATION OF INTEGRATED CIRCUITS 审中-公开

    公开(公告)号：US20190102500A1

    公开(公告)日：2019-04-04

    申请号：US15721195

    申请日：2017-09-29

    Applicant: Intel Corporation

    Inventor： Byron Sinclair ,  John Freeman

    IPC: G06F17/50 ,  G06F9/45 ,  G06F9/445

    Abstract: Methods and apparatus for performing profile-guided optimization of integrated circuit hardware are provided. Circuit design tools may receive a source code and compile the source code to generate a hardware description. The hardware description may include profiling blocks configured to measure useful information required for optimization. The hardware description may then be simulated to gather profiling data. The circuit design tools may then analyze the gathered profiling data to identify additional opportunities for hardware optimization. The source code may then be modified based on the analysis of the profiling data to produce a smaller and faster hardware that is better suited to the application.

    Fast CAD Compilation Through Coarse Macro Lowering
    3.
    发明公开
    Fast CAD Compilation Through Coarse Macro Lowering 审中-公开

    公开(公告)号：US20240020449A1

    公开(公告)日：2024-01-18

    申请号：US18475512

    申请日：2023-09-27

    Applicant: Intel Corporation

    Inventor： Byron Sinclair ,  Deshanand P. Singh ,  Gregg William Baeckler ,  Mahesh A. Iyer ,  Michael Kinsner ,  Chengping Liang ,  Victor Tzi-on Zhang

    IPC: G06F30/347

    CPC classification number: G06F30/347

    Abstract: Systems or methods of the present disclosure may provide a library including multiple macros that may be pre-compiled prior to implementation of the design. For example, a design may be mapped to one or more macros in the library, and the one or more macros may be placed into and routed between a portion of a region, one region, one or more regions of the integrated circuit device to implement the design. Since the macros may be pre-compiled, compilation time experienced by the designer may correspond to the placement and routing of the one or more macros, which may be less than compilation time for fine-grained operations. The pre-compiled logic within the macros may be set using a lookup table mask to set and/or adjust a functionality of the macro. Additionally or alternatively, the place and route operation may be performed at finer granularities to reduce bottle necks.

    METHODS AND APPARATUS FOR PROFILE-GUIDED OPTIMIZATION OF INTEGRATED CIRCUITS
    4.
    发明公开
    METHODS AND APPARATUS FOR PROFILE-GUIDED OPTIMIZATION OF INTEGRATED CIRCUITS 审中-公开

    公开(公告)号：US20230342531A1

    公开(公告)日：2023-10-26

    申请号：US18311886

    申请日：2023-05-03

    Applicant: Intel Corporation

    Inventor： Byron Sinclair ,  John Freeman

    IPC: G06F30/39 ,  G06F8/41 ,  G06F30/20

    CPC classification number: G06F30/39 ,  G06F8/41 ,  G06F8/4434 ,  G06F30/20 ,  G06F8/65

    Abstract: Methods and apparatus for performing profile-guided optimization of integrated circuit hardware are provided. Circuit design tools may receive a source code and compile the source code to generate a hardware description. The hardware description may include profiling blocks configured to measure useful information required for optimization. The hardware description may then be simulated to gather profiling data. The circuit design tools may then analyze the gathered profiling data to identify additional opportunities for hardware optimization. The source code may then be modified based on the analysis of the profiling data to produce a smaller and faster hardware that is better suited to the application.

    Methods and apparatus for using load and store addresses to resolve memory dependencies
    8.
    发明授权
    Methods and apparatus for using load and store addresses to resolve memory dependencies 有权

    公开(公告)号：US11379242B2

    公开(公告)日：2022-07-05

    申请号：US15637637

    申请日：2017-06-29

    Applicant: Intel Corporation

    Inventor： Andrei Mihai Hagiescu Miriste ,  Byron Sinclair ,  Joseph Garvey

    IPC: G06F9/38 ,  G06F9/48 ,  G06F9/30

    Abstract: An integrated circuit may include elastic datapaths or pipelines, through which software threads or iterations of loops, may be executed. Throttling circuitry may be coupled along an elastic pipeline in the integrated circuit. The throttling circuitry may include dependency detection circuitry that dynamically detect memory dependency issues that may arise during runtime. To mitigate these dependency issues, the throttling circuitry may assert stall signals to upstream stages in the pipeline. Additionally, the throttling circuitry may control the pipeline to resolve a store operation prior to a corresponding load operation in order to avoid store/load conflicts. In an embodiment, the throttling circuitry may include a validator circuit, a rewind block, a revert block, and a flush block. The throttling circuitry may pass speculative iterations through the rewind block, and later validate the speculative iterations using the validator block.

    METHODS AND APPARATUS FOR HANDLING RUNTIME MEMORY DEPENDENCIES
    9.
    发明申请
    METHODS AND APPARATUS FOR HANDLING RUNTIME MEMORY DEPENDENCIES 审中-公开

    公开(公告)号：US20190004804A1

    公开(公告)日：2019-01-03

    申请号：US15637637

    申请日：2017-06-29

    Applicant: Intel Corporation

    Inventor： Andrei Mihai Hagiescu Miriste ,  Byron Sinclair ,  Joseph Garvey

    IPC: G06F9/38 ,  G06F9/48 ,  G06F9/30

    Abstract: An integrated circuit may include elastic datapaths or pipelines, through which software threads or iterations of loops, may be executed. Throttling circuitry may be coupled along an elastic pipeline in the integrated circuit. The throttling circuitry may include dependency detection circuitry that dynamically detect memory dependency issues that may arise during runtime. To mitigate these dependency issues, the throttling circuitry may assert stall signals to upstream stages in the pipeline.Additionally, the throttling circuitry may control the pipeline to resolve a store operation prior to a corresponding load operation in order to avoid store/load conflicts. In an embodiment, the throttling circuitry may include a validator circuit, a rewind block, a revert block, and a flush block. The throttling circuitry may pass speculative iterations through the rewind block, and later validate the speculative iterations using the validator block.

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