Invention Application
- Patent Title: LINER RECESS FOR FULLY ALIGNED VIA
-
Application No.: US15647977Application Date: 2017-07-12
-
Publication No.: US20190019726A1Publication Date: 2019-01-17
- Inventor: Errol Todd RYAN , Sean Xuan LIN
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/522 ; H01L23/532 ; H01L23/528

Abstract:
Devices and methods of fabricating devices are provided. One method includes: obtaining an intermediate semiconductor device having a dielectric layer, an insulating layer, and a plurality of metal lines, including a liner material and a first metal material; recessing the metal material of each metal line forming a set of cavities; filling the cavities with a protective cap; etching the protective cap and the liner material in the set of cavities; depositing a plurality of dielectric caps in the set of cavities; depositing an interlayer dielectric layer over the insulating layer and the plurality of dielectric caps; patterning a via in the interlayer dielectric layer; and depositing a lining and a second metal material in the interconnect area; wherein the second metal material is electrically insulated from the first metal in at least one of the plurality of metal lines.
Public/Granted literature
- US10181421B1 Liner recess for fully aligned via Public/Granted day:2019-01-15
Information query
IPC分类: