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    LINER RECESS FOR FULLY ALIGNED VIA
    4.
    发明申请
    LINER RECESS FOR FULLY ALIGNED VIA 审中-公开

    公开(公告)号：US20190019726A1

    公开(公告)日：2019-01-17

    申请号：US15647977

    申请日：2017-07-12

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Errol Todd RYAN ,  Sean Xuan LIN

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

    Abstract: Devices and methods of fabricating devices are provided. One method includes: obtaining an intermediate semiconductor device having a dielectric layer, an insulating layer, and a plurality of metal lines, including a liner material and a first metal material; recessing the metal material of each metal line forming a set of cavities; filling the cavities with a protective cap; etching the protective cap and the liner material in the set of cavities; depositing a plurality of dielectric caps in the set of cavities; depositing an interlayer dielectric layer over the insulating layer and the plurality of dielectric caps; patterning a via in the interlayer dielectric layer; and depositing a lining and a second metal material in the interconnect area; wherein the second metal material is electrically insulated from the first metal in at least one of the plurality of metal lines.

    METHOD FOR RECESSING A CARBON-DOPED LAYER OF A SEMICONDUCTOR STRUCTURE
    5.
    发明申请
    METHOD FOR RECESSING A CARBON-DOPED LAYER OF A SEMICONDUCTOR STRUCTURE 审中-公开
    用于记录半导体结构的碳掺杂层的方法

    公开(公告)号：US20160163559A1

    公开(公告)日：2016-06-09

    申请号：US14812046

    申请日：2015-07-29

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Errol Todd RYAN

    IPC: H01L21/3105 ,  H01L29/78 ,  H01L29/06 ,  H01L21/311 ,  H01L29/66

    CPC classification number: H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/76826 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

    Abstract: Semiconductor structure and methods of fabrication thereof are provided which includes, for instance, providing a carbon-doped material layer within a recess of a semiconductor structure; removing, in part, carbon from the carbon-doped material layer to obtain, at least in part, a carbon-depleted region thereof, the carbon-depleted region having a modified etch property with an increased etch rate compared to an etch rate of the carbon-doped material layer; and recessing the carbon-depleted region of the carbon-doped material layer by an etching process, with the carbon-depleted region being recessed based upon, in part, the modified etch property of the carbon-depleted region.

    Abstract translation: 提供半导体结构及其制造方法，其包括例如在半导体结构的凹部内提供碳掺杂材料层; 部分地从碳掺杂材料层去除碳，以至少部分地获得其贫碳区域，具有改进的蚀刻性能的碳贫乏区域与蚀刻速率相比具有增加的蚀刻速率 碳掺杂材料层; 并且通过蚀刻工艺使碳掺杂材料层的碳贫乏区域凹陷，其中碳贫乏区域部分地基于碳贫乏区域的改性蚀刻性质而凹陷。

    METHODS OF SEMICONDUCTOR CONTAMINANT REMOVAL USING SUPERCRITICAL FLUID
    6.
    发明申请
    METHODS OF SEMICONDUCTOR CONTAMINANT REMOVAL USING SUPERCRITICAL FLUID 审中-公开
    使用超临界流体的半导体污染物去除方法

    公开(公告)号：US20140353805A1

    公开(公告)日：2014-12-04

    申请号：US13903618

    申请日：2013-05-28

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Errol Todd RYAN ,  Moosung M. CHAE ,  Larry ZHAO ,  Kunaljeet TANWAR ,  Nicholas Vincent LICAUSI ,  Christian WITT ,  Ailian ZHAO ,  Ming HE ,  Sean X. LIN ,  Xunyuan ZHANG

    IPC: H01L21/3105 ,  H01L23/00

    CPC classification number: H01L21/02101 ,  H01L21/02063 ,  H01L21/76814

    Abstract: A process is provided for the removal of contaminants from a semiconductor device, for example, removing contaminants from pores of an ultra-low k film. In one aspect, a method includes: providing a dielectric layer with contaminant-containing pores and exposing the dielectric layer to a supercritical fluid. The supercritical fluid can dissolve and remove the contaminants. In another aspect, an intermediate semiconductor device structure is provided that contains a dielectric layer with contaminant-containing pores and a supercritical fluid within the pores. In another aspect, a semiconductor device structure with a dielectric layer containing uncontaminated pores is provided.

    Abstract translation: 提供了用于从半导体器件去除污染物的方法，例如从超低k膜的孔中除去污染物。 一方面，一种方法包括：向电介质层提供含有污染物的孔，并将介电层暴露于超临界流体。 超临界流体可以溶解和去除污染物。 在另一方面，提供了一种中间半导体器件结构，其包含具有含污染孔的电介质层和孔内的超临界流体。 另一方面，提供了具有含有未污染孔的电介质层的半导体器件结构。

    DEVICES AND METHODS OF FORMING LOW RESISTIVITY NOBLE METAL INTERCONNECT
    7.
    发明申请
    DEVICES AND METHODS OF FORMING LOW RESISTIVITY NOBLE METAL INTERCONNECT 审中-公开

    公开(公告)号：US20180040555A1

    公开(公告)日：2018-02-08

    申请号：US15785665

    申请日：2017-10-17

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xunyuan ZHANG ,  Frank W. MONT ,  Errol Todd RYAN

    IPC: H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L21/285 ,  H01L23/528

    Abstract: Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.

    DEVICES AND METHODS OF FORMING ASYMMETRIC LINE/SPACE WITH BARRIERLESS METALLIZATION
    8.
    发明申请
    DEVICES AND METHODS OF FORMING ASYMMETRIC LINE/SPACE WITH BARRIERLESS METALLIZATION 有权

    公开(公告)号：US20170365509A1

    公开(公告)日：2017-12-21

    申请号：US15182794

    申请日：2016-06-15

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Errol Todd RYAN ,  Nicholas Vincent LICAUSI

    IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02

    CPC classification number: H01L21/76814 ,  H01L21/02126 ,  H01L21/31111 ,  H01L21/76825 ,  H01L21/76826

    Abstract: Devices and methods of fabricating integrated circuit devices for forming assymetric line/space with barrierless metallization are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate, a dielectric matrix, and a hardmask, the dielectric matrix including a set of trenches etched into the dielectric matrix and a set of dielectric fins comprising the dielectric matrix, wherein the set of trenches and the set of dielectric fins are of equal width; damaging an inner surface of each trench of the set of trenches; etching the damaged material of the trenches removing the damaged material of the dielectric matrix; removing the hardmask; and metallizing the trenches by depositing a metal directly on the dielectric matrix with no barrier between the metal and the dielectric matrix after the etching. Also disclosed is an intermediate device formed by the method.

    METHOD FOR DEFINING AN ISOLATION REGION(S) OF A SEMICONDUCTOR STRUCTURE
    10.
    发明申请
    METHOD FOR DEFINING AN ISOLATION REGION(S) OF A SEMICONDUCTOR STRUCTURE 有权
    用于定义半导体结构的隔离区域的方法

    公开(公告)号：US20160099168A1

    公开(公告)日：2016-04-07

    申请号：US14504479

    申请日：2014-10-02

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Errol Todd RYAN

    IPC: H01L21/762 ,  H01L21/265

    CPC classification number: H01L21/76224 ,  H01L21/02337 ,  H01L21/2236 ,  H01L21/26566

    Abstract: Methods for defining an isolation region of a semiconductor structure are provided. The method includes, for instance: providing a semiconductor structure with a recess therein; disposing an insulator layer conformally within the recess in the semiconductor structure to partially fill the recess; modifying at least one material property of the insulator layer to obtain a densified insulator layer within the recess, where the modifying reduces a thickness of the densified insulator layer compared to that of the insulator layer; and depositing at least one additional insulator layer within the recess over the densified insulator layer, where the densified insulator layer within the recess defines, at least in part, an isolation region of the semiconductor structure.

    Abstract translation: 提供了用于限定半导体结构的隔离区域的方法。 该方法包括例如：提供其中具有凹部的半导体结构; 在半导体结构中的凹部内共形布置绝缘体层以部分地填充凹部; 修改绝缘体层的至少一种材料性质以在凹陷内获得致密化的绝缘体层，其中改性减少了与绝缘体层相比较的致密绝缘体层的厚度; 以及在所述凹陷内的所述致密绝缘体层上沉积至少一个额外的绝缘体层，其中所述凹陷内的所述致密绝缘体层至少部分地限定所述半导体结构的隔离区域。

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