Invention Application
- Patent Title: TRANSISTOR GATE-CHANNEL ARRANGEMENTS
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Application No.: US16080101Application Date: 2016-03-30
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Publication No.: US20190058043A1Publication Date: 2019-02-21
- Inventor: Gilbert W. Dewey , Rafael Rios , Shriram Shivaraman , Marko Radosavljevic , Kent E. Millard , Marc C. French , Van H. Le
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- International Application: PCT/US2016/024828 WO 20160330
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H01L29/221 ; H01L29/423 ; H01L29/417 ; H01L29/66 ; H01L29/78

Abstract:
Disclosed herein are transistor gate-channel arrangements, and related methods and devices. For example, in some embodiments, a transistor gate-channel arrangement may include a channel material and a transistor gate stack. The transistor gate stack may include a gate electrode material, a high-k dielectric disposed between the gate electrode material and the channel material, and indium gallium zinc oxide (IGZO) disposed between the high-k dielectric material and the channel material.
Information query
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